[siemens/jailhouse] a86317: core: pci: Fix MMCONFIG handling
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Sep 18, 2015, 12:10:10 PM9/18/15
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Branch: refs/heads/next
Home: https://github.com/siemens/jailhouse
Commit: a8631704fa3cb2f519f78aeb60e90de0476aa8ad
https://github.com/siemens/jailhouse/commit/a8631704fa3cb2f519f78aeb60e90de0476aa8ad
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-18 (Fri, 18 Sep 2015)
Changed paths:
M hypervisor/pci.c
Log Message:
-----------
core: pci: Fix MMCONFIG handling
Reorder the initialization in pci_init so that MMCONFIG is set up before
pci_cell_init is invoked for the root cell. Calling pci_cell_init
earlier has the undesired effect that the MMCONFIG region is not
registered for the root cell, and all related accesses will fail with
generic MMIO errors.
This is a regression of e17d52525d.
Reported-by: Yijun Zhu <zhuy...@huawei.com>
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 24a76e612d5e834a5fa8f6799e230b4e7bdaffe9
https://github.com/siemens/jailhouse/commit/24a76e612d5e834a5fa8f6799e230b4e7bdaffe9
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-18 (Fri, 18 Sep 2015)
Changed paths:
M hypervisor/pci.c
Log Message:
-----------
core: pci: Fix format string of MMCONFIG error reporting
The config space address was not printed.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: cb6f16c8a54b9dcbcebe91a3fe1ab3cc5b2a2de1
https://github.com/siemens/jailhouse/commit/cb6f16c8a54b9dcbcebe91a3fe1ab3cc5b2a2de1
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-18 (Fri, 18 Sep 2015)
Changed paths:
M hypervisor/arch/x86/vmx.c
Log Message:
-----------
x86: vmx: Micro-cleanup in vcpu_vendor_cell_init
Return the error code directly instead of take the indirect route via
pre-initialized err variable. Avoids that some refactoring once destroys
this relationship.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 97f27cc8d578b06971a76be3ca73fd003160719a
https://github.com/siemens/jailhouse/commit/97f27cc8d578b06971a76be3ca73fd003160719a
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-18 (Fri, 18 Sep 2015)
Changed paths:
M hypervisor/arch/x86/include/asm/processor.h
M hypervisor/arch/x86/paging.c
M hypervisor/arch/x86/setup.c
M hypervisor/arch/x86/svm.c
M hypervisor/arch/x86/vcpu.c
M hypervisor/arch/x86/vmx.c
Log Message:
-----------
x86: Add sub-leaf selection parameter to cpuid_*
This allows to call cpuid also on specific sub-leaves. Will be used
first for CAT.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 3998ef067a935a032d8a088c94e4a54d1623f371
https://github.com/siemens/jailhouse/commit/3998ef067a935a032d8a088c94e4a54d1623f371
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-18 (Fri, 18 Sep 2015)
Changed paths:
M hypervisor/arch/x86/vmx.c
Log Message:
-----------
x86: vmx: Block write access to CAT MSRs
Make sure the cells cannot mess around with them, modifying the
configuration the hypervisor chose.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 8973fa88a9ce2ede65f28efa4dc7546d5cb1cf50
https://github.com/siemens/jailhouse/commit/8973fa88a9ce2ede65f28efa4dc7546d5cb1cf50
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-18 (Fri, 18 Sep 2015)
Changed paths:
M hypervisor/include/jailhouse/cell-config.h
M tools/jailhouse-cell-linux
Log Message:
-----------
core, tools: Introduce cache regions to the cell configuration
Allow to specify regions of caches so that the hypervisor can partition
their usage accordingly whenever the hardware supports this.
The specification of their start location and sizes depend on the
architecture specific partitioning support. So far, L1-L3 cache types
are definable (of which Intel's CAT will only support L3). As with
memory regions, caches are usually taken from the root cell on non-root
cell creation, but they can also be declared as shared with the root
cell.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: d47bd51366341b0c452b667a9979fa8574391e32
https://github.com/siemens/jailhouse/commit/d47bd51366341b0c452b667a9979fa8574391e32
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-18 (Fri, 18 Sep 2015)
Changed paths:
M hypervisor/arch/x86/Makefile
A hypervisor/arch/x86/cat-stubs.c
A hypervisor/arch/x86/cat.c
M hypervisor/arch/x86/control.c
A hypervisor/arch/x86/include/asm/cat.h
M hypervisor/arch/x86/include/asm/cell.h
M hypervisor/arch/x86/include/asm/percpu.h
M hypervisor/arch/x86/include/asm/processor.h
M hypervisor/arch/x86/setup.c
Log Message:
-----------
x86: Introduce Cache Allocation Technology support for Intel CPUs
CAT is a CPU feature first added to Xeon D and certain Xeon E5 v3
processors. It so far allows to specify access restrictions to the L3
cache, including complete isolation between different entities.
This adds CAT control to Jailhouse on a per-cell level. The user is free
to specify a contiguous access mask for each cell, use that mask
exclusively (typical case), share any overlaps with the root cell
(JAILHOUSE_CACHE_ROOTSHARED), or simply use the root cell mask. If
nothing else is specified, the root cell uses the full cache (until
non-root cells shrink it).
Due to the hardware-induced requirement to have a contiguous bitmask,
shrinking the root mask on cell creation and extending it again on
destruction is not trivial.
When creating a new cell, we may punch a whole into the root mask. In
that case, we also subtract the smaller remaining half from it.
When restoring the root mask on cell destruction, we choose a simple
algorithm that first collects all released bits in a combined mask, then
tries to merge that mask bit-wise with the current root cell mask. On
success we restart the freed mask walk to ensure that all contiguous
bits are merged.
A lot of complication, despite we already require explicit mask
allocation. Let's just hope that there is a noteworthy benefit in
restricting CAT bitmasks in hardware this way.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 76301c11f403a867d263f2e49eee974fec3a70db
https://github.com/siemens/jailhouse/commit/76301c11f403a867d263f2e49eee974fec3a70db
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-18 (Fri, 18 Sep 2015)
Changed paths:
M configs/apic-demo.c
M configs/linux-x86-demo.c
M configs/tiny-demo.c
Log Message:
-----------
configs: Add cache region to x86 demo cells
Assuming we have more than 4 units of L3 cache on systems that support
L3 partitioning, assign the first unit (e.g. 1 MB on a Xeon D 1540) to
apic-demo, the second to tiny-demo and the succeeding 2 to the non-root
Linux config. The latter is supposed to improve the Linux cell latencies
while the former two are not (they are expected to stay in L1/L2 due to
their sizes) but serve as test cases for the partitioning management
logic.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 8fd7b6f3fc23e860903d99e386f32ef6cd464477
https://github.com/siemens/jailhouse/commit/8fd7b6f3fc23e860903d99e386f32ef6cd464477
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-18 (Fri, 18 Sep 2015)
Changed paths:
M TODO.md
Log Message:
-----------
TODO: Remove CAT item
Feature is now available.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Compare: https://github.com/siemens/jailhouse/compare/47f24159ba42...8fd7b6f3fc23
Home: https://github.com/siemens/jailhouse
Commit: a8631704fa3cb2f519f78aeb60e90de0476aa8ad
https://github.com/siemens/jailhouse/commit/a8631704fa3cb2f519f78aeb60e90de0476aa8ad
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-18 (Fri, 18 Sep 2015)
Changed paths:
M hypervisor/pci.c
Log Message:
-----------
core: pci: Fix MMCONFIG handling
Reorder the initialization in pci_init so that MMCONFIG is set up before
pci_cell_init is invoked for the root cell. Calling pci_cell_init
earlier has the undesired effect that the MMCONFIG region is not
registered for the root cell, and all related accesses will fail with
generic MMIO errors.
This is a regression of e17d52525d.
Reported-by: Yijun Zhu <zhuy...@huawei.com>
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 24a76e612d5e834a5fa8f6799e230b4e7bdaffe9
https://github.com/siemens/jailhouse/commit/24a76e612d5e834a5fa8f6799e230b4e7bdaffe9
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-18 (Fri, 18 Sep 2015)
Changed paths:
M hypervisor/pci.c
Log Message:
-----------
core: pci: Fix format string of MMCONFIG error reporting
The config space address was not printed.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: cb6f16c8a54b9dcbcebe91a3fe1ab3cc5b2a2de1
https://github.com/siemens/jailhouse/commit/cb6f16c8a54b9dcbcebe91a3fe1ab3cc5b2a2de1
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-18 (Fri, 18 Sep 2015)
Changed paths:
M hypervisor/arch/x86/vmx.c
Log Message:
-----------
x86: vmx: Micro-cleanup in vcpu_vendor_cell_init
Return the error code directly instead of take the indirect route via
pre-initialized err variable. Avoids that some refactoring once destroys
this relationship.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 97f27cc8d578b06971a76be3ca73fd003160719a
https://github.com/siemens/jailhouse/commit/97f27cc8d578b06971a76be3ca73fd003160719a
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-18 (Fri, 18 Sep 2015)
Changed paths:
M hypervisor/arch/x86/include/asm/processor.h
M hypervisor/arch/x86/paging.c
M hypervisor/arch/x86/setup.c
M hypervisor/arch/x86/svm.c
M hypervisor/arch/x86/vcpu.c
M hypervisor/arch/x86/vmx.c
Log Message:
-----------
x86: Add sub-leaf selection parameter to cpuid_*
This allows to call cpuid also on specific sub-leaves. Will be used
first for CAT.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 3998ef067a935a032d8a088c94e4a54d1623f371
https://github.com/siemens/jailhouse/commit/3998ef067a935a032d8a088c94e4a54d1623f371
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-18 (Fri, 18 Sep 2015)
Changed paths:
M hypervisor/arch/x86/vmx.c
Log Message:
-----------
x86: vmx: Block write access to CAT MSRs
Make sure the cells cannot mess around with them, modifying the
configuration the hypervisor chose.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 8973fa88a9ce2ede65f28efa4dc7546d5cb1cf50
https://github.com/siemens/jailhouse/commit/8973fa88a9ce2ede65f28efa4dc7546d5cb1cf50
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-18 (Fri, 18 Sep 2015)
Changed paths:
M hypervisor/include/jailhouse/cell-config.h
M tools/jailhouse-cell-linux
Log Message:
-----------
core, tools: Introduce cache regions to the cell configuration
Allow to specify regions of caches so that the hypervisor can partition
their usage accordingly whenever the hardware supports this.
The specification of their start location and sizes depend on the
architecture specific partitioning support. So far, L1-L3 cache types
are definable (of which Intel's CAT will only support L3). As with
memory regions, caches are usually taken from the root cell on non-root
cell creation, but they can also be declared as shared with the root
cell.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: d47bd51366341b0c452b667a9979fa8574391e32
https://github.com/siemens/jailhouse/commit/d47bd51366341b0c452b667a9979fa8574391e32
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-18 (Fri, 18 Sep 2015)
Changed paths:
M hypervisor/arch/x86/Makefile
A hypervisor/arch/x86/cat-stubs.c
A hypervisor/arch/x86/cat.c
M hypervisor/arch/x86/control.c
A hypervisor/arch/x86/include/asm/cat.h
M hypervisor/arch/x86/include/asm/cell.h
M hypervisor/arch/x86/include/asm/percpu.h
M hypervisor/arch/x86/include/asm/processor.h
M hypervisor/arch/x86/setup.c
Log Message:
-----------
x86: Introduce Cache Allocation Technology support for Intel CPUs
CAT is a CPU feature first added to Xeon D and certain Xeon E5 v3
processors. It so far allows to specify access restrictions to the L3
cache, including complete isolation between different entities.
This adds CAT control to Jailhouse on a per-cell level. The user is free
to specify a contiguous access mask for each cell, use that mask
exclusively (typical case), share any overlaps with the root cell
(JAILHOUSE_CACHE_ROOTSHARED), or simply use the root cell mask. If
nothing else is specified, the root cell uses the full cache (until
non-root cells shrink it).
Due to the hardware-induced requirement to have a contiguous bitmask,
shrinking the root mask on cell creation and extending it again on
destruction is not trivial.
When creating a new cell, we may punch a whole into the root mask. In
that case, we also subtract the smaller remaining half from it.
When restoring the root mask on cell destruction, we choose a simple
algorithm that first collects all released bits in a combined mask, then
tries to merge that mask bit-wise with the current root cell mask. On
success we restart the freed mask walk to ensure that all contiguous
bits are merged.
A lot of complication, despite we already require explicit mask
allocation. Let's just hope that there is a noteworthy benefit in
restricting CAT bitmasks in hardware this way.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 76301c11f403a867d263f2e49eee974fec3a70db
https://github.com/siemens/jailhouse/commit/76301c11f403a867d263f2e49eee974fec3a70db
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-18 (Fri, 18 Sep 2015)
Changed paths:
M configs/apic-demo.c
M configs/linux-x86-demo.c
M configs/tiny-demo.c
Log Message:
-----------
configs: Add cache region to x86 demo cells
Assuming we have more than 4 units of L3 cache on systems that support
L3 partitioning, assign the first unit (e.g. 1 MB on a Xeon D 1540) to
apic-demo, the second to tiny-demo and the succeeding 2 to the non-root
Linux config. The latter is supposed to improve the Linux cell latencies
while the former two are not (they are expected to stay in L1/L2 due to
their sizes) but serve as test cases for the partitioning management
logic.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 8fd7b6f3fc23e860903d99e386f32ef6cd464477
https://github.com/siemens/jailhouse/commit/8fd7b6f3fc23e860903d99e386f32ef6cd464477
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-18 (Fri, 18 Sep 2015)
Changed paths:
M TODO.md
Log Message:
-----------
TODO: Remove CAT item
Feature is now available.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Compare: https://github.com/siemens/jailhouse/compare/47f24159ba42...8fd7b6f3fc23
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