[siemens/jailhouse] 645408: driver: ioremap the hypervisor firmware to any ker...
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3 de fev. de 2016, 15:18:2503/02/2016
para jailho...@googlegroups.com
Branch: refs/heads/wip/arm64
Home: https://github.com/siemens/jailhouse
Commit: 6454087832d4d9e9fbe989f533e5f8a91a717809
https://github.com/siemens/jailhouse/commit/6454087832d4d9e9fbe989f533e5f8a91a717809
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M driver/main.c
M hypervisor/arch/arm/include/asm/jailhouse_hypercall.h
M hypervisor/arch/x86/include/asm/jailhouse_hypercall.h
M hypervisor/setup.c
Log Message:
-----------
driver: ioremap the hypervisor firmware to any kernel address
At the moment the Linux driver maps the Jailhouse binary to
JAILHOUSE_BASE. The underlying assumption is that Linux may map the
firmware (in the Linux kernel space), to the same virtual address it
has been built to run from.
This assumption is unworkable on ARMv8 processors running in AArch64
mode. Kernel memory is allocated in a high address region, that is
not addressable from EL2, where the hypervisor will run from.
This patch removes the assumption, by introducing the
JAILHOUSE_BORROW_ROOT_PT define, which describes the behavior of the
current architectures.
We also turn the entry point in the header, into an offset from the
Jailhouse load address, so we can enter the image regardless of
where it will be mapped.
On AArch64, JAILHOUSE_BASE will be the physical address the
hypervisor will be loaded to. This way, Jailhouse will run with
identity mapping in EL2. The Linux driver sets the address to the
debug UART accordingly.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: acea65443ab0c4fbdc44696c6faea79b8a45e3a4
https://github.com/siemens/jailhouse/commit/acea65443ab0c4fbdc44696c6faea79b8a45e3a4
Author: Dmitry Voytik <dmitry...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M driver/cell.c
M driver/main.c
Log Message:
-----------
driver: sync I-cache, D-cache and memory
Syncronize I-cache with D-cache after loading the hypervisor
image or a cell image. This must be done in arm64 according to
ARMv8 ARM spec. See page 1712, D3.4.6 "Non-cacheable accesses
and instruction caches".
This patch fixes coherency problems observed on real HW targets.
On x86 this operation is a NOP.
Signed-off-by: Dmitry Voytik <dmitry...@huawei.com>
Commit: ea171ff353fbdecc66b28089af98d10c11d2983b
https://github.com/siemens/jailhouse/commit/ea171ff353fbdecc66b28089af98d10c11d2983b
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/paging.h
M hypervisor/arch/arm/irqchip.c
M hypervisor/arch/arm/mmu_cell.c
M hypervisor/arch/x86/apic.c
M hypervisor/arch/x86/include/asm/paging.h
M hypervisor/arch/x86/ioapic.c
M hypervisor/arch/x86/svm.c
M hypervisor/arch/x86/vmx.c
M hypervisor/arch/x86/vtd.c
M hypervisor/control.c
M hypervisor/include/jailhouse/paging.h
M hypervisor/mmio.c
M hypervisor/paging.c
M hypervisor/pci.c
M hypervisor/pci_ivshmem.c
Log Message:
-----------
core: reimplement page_alloc to allow aligned allocations
The function page_alloc allows us to allocate any number of
pages, however they will always be aligned on page boundaries.
The new page_alloc implementation takes an extra bool align
parameter, which allows us to allocate N pages that will be
aligned by N * PAGE_SIZE. N needs to be a power of two.
This will be used on the AArch64 port of Jailhouse to support
physical address ranges from 40 to 44 bits: in these
configurations, the initial page table level may take up
multiple consecutive pages.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 98283eebd6b46fa64b7a1e68465e54bdb65cdad2
https://github.com/siemens/jailhouse/commit/98283eebd6b46fa64b7a1e68465e54bdb65cdad2
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/irqchip.h
Log Message:
-----------
hypervisor: arm: pass SPIs with large ids to the root cell
The current design for cell configuration files, defines the SPIs
to be passed to a cell as 64 bit bitmap. In order to use Jailhouse
on targets that have SPI ids larger than 64, we need to work
around this limitation.
Pass large SPIs to the root cell for now. A permanent solution to
this problem will need to tackle the cell configuration format.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 6286f3b676639d1692e8668acbc0c4ac92111cd1
https://github.com/siemens/jailhouse/commit/6286f3b676639d1692e8668acbc0c4ac92111cd1
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm/lib.c
Log Message:
-----------
hypervisor: arm: phys_processor_id should return logical id
Currently the function phys_processor_id identifies the current
CPU by reading the MPIDR register. However, on systems with
multiple implemented affinity levels, the scheme used by this
register is hierarchical and does not correspond to the logical
IDs allocated to CPUs.
Change phys_processor_id to return the logical CPU id, so we
don't run into problems when we start implementing support for
affinity levels.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 40b4cc1e492f9638c6de211c728f96824c40f264
https://github.com/siemens/jailhouse/commit/40b4cc1e492f9638c6de211c728f96824c40f264
Author: Claudio Fontana <claudio...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm/lib.c
M hypervisor/lib.c
Log Message:
-----------
core: lib: move memcpy implementation from the ARM port
Move the memcpy implementation from the ARM port,
to the core library.
Signed-off-by: Claudio Fontana <claudio...@huawei.com>
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
[antonios...@huawei.com: removed all signs of weakness!]
Commit: c71954152339663698dea2394e976aa67d6bdec2
https://github.com/siemens/jailhouse/commit/c71954152339663698dea2394e976aa67d6bdec2
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm/control.c
M hypervisor/arch/arm/lib.c
Log Message:
-----------
hypervisor: arm: move arm_cpu_virt2phys to lib.c
Putting arm_cpu_virt2phys under arch/arm/lib.c is a little
more consistent (it can become friends with phys_processor_id),
and we'll benefit by sharing the implementation with AArch64.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: cc8ee2b83c4b1f71aac50d5637d89116cf91e1c2
https://github.com/siemens/jailhouse/commit/cc8ee2b83c4b1f71aac50d5637d89116cf91e1c2
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/control.h
M hypervisor/arch/arm/include/asm/percpu.h
M hypervisor/arch/arm/lib.c
M hypervisor/arch/arm/psci.c
M hypervisor/arch/arm/setup.c
Log Message:
-----------
hypervisor: arm: psci: support multiple affinity levels in MPIDR
PSCI actually takes CPU parameters by the MPIDR id, which may
differ from the logical id of the CPU. This patch is the first step
into properly handling the CPU affinity levels in the MPIDR.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 942c4063eae4be3644bfa3bff9e196a32dcbdab9
https://github.com/siemens/jailhouse/commit/942c4063eae4be3644bfa3bff9e196a32dcbdab9
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/psci.h
Log Message:
-----------
hypervisor: arm: make IS_PSCI_FN macro more restrictive
The previous version of the macro allows for more false positives
than necessary.
The SVC32 and SVC64 versions of the PSCI function ids differ only
on one bit. Mask this bit from the function id prefix and compare.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 6761af3953ede05e3bc86e6c2dab56f439e4b9e4
https://github.com/siemens/jailhouse/commit/6761af3953ede05e3bc86e6c2dab56f439e4b9e4
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/processor.h
M hypervisor/arch/arm/mmu_cell.c
Log Message:
-----------
hypervisor: arm: hide TLB flush behind a macro
Hide TLB flushes issues by the MMU code behind a macro, so we can
increase our chances of reusing some of this code.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 04ed1c18f11541fef7482c0979c92b75f9c6ee94
https://github.com/siemens/jailhouse/commit/04ed1c18f11541fef7482c0979c92b75f9c6ee94
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/paging.h
M hypervisor/arch/arm/mmu_cell.c
Log Message:
-----------
hypervisor: arm: put the value of VTCR for cells in a define
We can reuse the code under hypervisor/arch/arm/mmu_cell.c for the
AArch64 port, save for the value we use for the VTCRL. AArch64 will
need in addition to the flags set by the AArch32 port, to set the
size of the address space to 40 bits; at least initially, until we
implement the new MMU features in ARMv8.
We put this behind a define in asm/paging.h to allow this reuse.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: f2e5bb1f6ea4f9dcc343776cdf444bc4d5c0ae62
https://github.com/siemens/jailhouse/commit/f2e5bb1f6ea4f9dcc343776cdf444bc4d5c0ae62
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A hypervisor/arch/arm64/include/asm/sysregs.h
Log Message:
-----------
hypervisor: arm64: add sysregs helper macros
On the AArch32 port of Jailhouse, the arm_write_sysreg and
arm_read_sysreg macros are used to access the system registers.
Implementing these helpers on AArch64 allows to approach some low
hanging fruit when looking for code to reuse from the AArch32 port.
On AArch64 we always get a u64 value from a system register, while
on AArch32 it might be either u32 or u64. We need to look at the
users of this macro on a case by case basis and see if it makes
sense to reuse code.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 856c33d1c2464aee8ad6d16dea0cf40b1e7b6cdf
https://github.com/siemens/jailhouse/commit/856c33d1c2464aee8ad6d16dea0cf40b1e7b6cdf
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A hypervisor/arch/arm64/include/asm/processor.h
Log Message:
-----------
hypervisor: arm64: add asm/processor.h header for AArch64
Add an initial asm/processor.h header for AArch64. This header is
loosely based on the version for AArch32, but we have kept the stuff
that we use.
More correctness checking still needs to be done.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 8331a206780dcdc86fd6c906f2d12b04e156e4e4
https://github.com/siemens/jailhouse/commit/8331a206780dcdc86fd6c906f2d12b04e156e4e4
Author: Dmitry Voytik <dmitry...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A hypervisor/arch/arm64/include/asm/control.h
Log Message:
-----------
hypervisor: arm64: add control.h header file
Add the header file control.h to the AArch64 port of Jailhouse.
Signed-off-by: Dmitry Voytik <dmitry...@huawei.com>
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
[antonios...@huawei.com: split off as a separate patch]
Commit: 3a38f6e5f88534ef089e908108ab6c0be9766a7c
https://github.com/siemens/jailhouse/commit/3a38f6e5f88534ef089e908108ab6c0be9766a7c
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A hypervisor/arch/arm64/include/asm/paging.h
Log Message:
-----------
hypervisor: arm64: add definitions for the AArch64 page table format
The AArch64 page table format is very similar, almost identical to
the AArch32 page table format. Add a header file for the AArch64 page
table format, based on the AArch32 implementation.
AArch64 introduces an extra level of page tables, for a total of
four, and support for different translation granule sizes. Disabling
the level zero of the page tables, and using a granule size of 4Kb,
results in an identical page table format with AArch32. With these
parameters, we can address 39 bits of memory.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 24ddab5f9db6a6d6d5330158d39e24494bdb17f0
https://github.com/siemens/jailhouse/commit/24ddab5f9db6a6d6d5330158d39e24494bdb17f0
Author: Dmitry Voytik <dmitry...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A hypervisor/arch/arm64/include/asm/types.h
Log Message:
-----------
hypervisor: arm64: add types.h
Add the asm/types.h header file, which defines the size of the data
types.
Signed-off-by: Dmitry Voytik <dmitry...@huawei.com>
Commit: c5e85c28b814e45fd6686589059c31cdfc5932e9
https://github.com/siemens/jailhouse/commit/c5e85c28b814e45fd6686589059c31cdfc5932e9
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A hypervisor/arch/arm64/include/asm/spinlock.h
Log Message:
-----------
hypervisor: arm64: spinlock implementation
Implement spinlocks for the hypervisor firmware, on AArch64.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 368d3bde2d0b858e6b15e329d01429bacddaec39
https://github.com/siemens/jailhouse/commit/368d3bde2d0b858e6b15e329d01429bacddaec39
Author: Claudio Fontana <claudio...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A hypervisor/arch/arm64/include/asm/bitops.h
Log Message:
-----------
arm64: implement bitops
implement set_bit, clear_bit, test_and_set_bit.
test_and_set_bit is used only in the panic_printk apparently,
while set_bit and clear_bit are used in page table handling code.
Signed-off-by: Claudio Fontana <claudio...@huawei.com>
Commit: d5c2fa9d56a89a47f85e8411dd1db4989f0b6e35
https://github.com/siemens/jailhouse/commit/d5c2fa9d56a89a47f85e8411dd1db4989f0b6e35
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A hypervisor/arch/arm64/include/asm/percpu.h
Log Message:
-----------
hypervisor: arm64: add percpu.h header file
Add the percpu.h header file for the AArch64 implementation. This is
the bare bones version of the header needed to compile a stub
hypervisor binary on AArch64. A lot of these fields could probably
be moved to an arch independent header.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: c823d30ee16e629932c7e94bff0c615e66512c01
https://github.com/siemens/jailhouse/commit/c823d30ee16e629932c7e94bff0c615e66512c01
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A hypervisor/arch/arm64/include/asm/cell.h
Log Message:
-----------
hypervisor: arm64: add cell.h header file
Add the initial cell.h header file needed to build on AArch64.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: e8161dc14826432c1811f3964933e2de3045d367
https://github.com/siemens/jailhouse/commit/e8161dc14826432c1811f3964933e2de3045d367
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A hypervisor/arch/arm64/include/asm/jailhouse_hypercall.h
Log Message:
-----------
hypervisor: arm64: add jailhouse_hypercall.h header file
Add the jailhouse_hypercall.h header file for AArch64. We will need
this also from the Linux side, in order to load Jailhouse in memory
and to issue hypercalls to an already loaded instance of the
hypervisor.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 8d2700d2418e3364f4c3c8c10111dd42255aac5c
https://github.com/siemens/jailhouse/commit/8d2700d2418e3364f4c3c8c10111dd42255aac5c
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/Makefile
A hypervisor/arch/arm64/Makefile
A hypervisor/arch/arm64/asm-defines.c
A hypervisor/arch/arm64/control.c
A hypervisor/arch/arm64/entry.S
M hypervisor/arch/arm64/include/asm/control.h
A hypervisor/arch/arm64/include/asm/head.h
M hypervisor/arch/arm64/include/asm/percpu.h
A hypervisor/arch/arm64/include/asm/platform.h
A hypervisor/arch/arm64/mmio.c
A hypervisor/arch/arm64/setup.c
A inmates/demos/arm64/Makefile
A inmates/lib/arm64/Makefile
A inmates/tools/arm64/Makefile
Log Message:
-----------
hypervisor: arm64: minimum stubs to allow building on AArch64
Add the minimum stub functions expected by the rest of the codebase
to enable building on AArch64. We may implement the missing AArch64
functionality from here.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 1b53808f991649609e5d682f528a0d60db92a0c1
https://github.com/siemens/jailhouse/commit/1b53808f991649609e5d682f528a0d60db92a0c1
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A configs/foundation-v8.c
M hypervisor/arch/arm64/include/asm/platform.h
Log Message:
-----------
core: add root cell configuration for the ARMv8 Foundation model
Add under config/foundation-v8.c a root cell configuration for the
ARMv8 Foundation model, so we can in use this target with Jailhouse.
We also add the neccessary parameters in asm/platform.h for this
model.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: ad763f7de20ea3a50b18470d24b6da1338cb9990
https://github.com/siemens/jailhouse/commit/ad763f7de20ea3a50b18470d24b6da1338cb9990
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A ci/jailhouse-config-amd-seattle.h
A configs/amd-seattle.c
M hypervisor/arch/arm/include/asm/uart_pl011.h
M hypervisor/arch/arm64/include/asm/platform.h
Log Message:
-----------
hypervisor: arm64: root cell configuration for the AMD Seattle
Add the root cell configuration and necessary headers to build
and run Jailhouse on the AMD Seattle development board.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 8c1acac3f02d7b71df7f1616416f68d0e948b4b5
https://github.com/siemens/jailhouse/commit/8c1acac3f02d7b71df7f1616416f68d0e948b4b5
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm64/entry.S
M hypervisor/arch/arm64/include/asm/percpu.h
Log Message:
-----------
hypervisor: arm64: implement entry code to the hypervisor firmware
Implement the entry point we will jump to after the Linux driver
loads the firmware to memory. Here we also set up a stack for the
hypervisor to use.
Unlike AArch32, we jump to EL2 as soon as we enter the hypervisor
binary.
To do this, we also set up temporary MMU mappings. We use just two
pages, to statically configure the MMU for identity mapping;
we need this in order to perform unaligned accesses from the
hypervisor binary during early initialization.
To generate the early page tables at build time, we need to know the
Jailhouse physical address, and the physical address of the debug
UART. We introduce this change of behaviour in AArch64, because in
this architecture we do not have the option of using the page tables
set up previously by Linux.
Reviewed for cache coherency correctness by Dmitry Voytik.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Signed-off-by: Dmitry Voytik <dmitry...@huawei.com>
Commit: fcfa82aa1bcb3bd9186377095635de105eec4d6e
https://github.com/siemens/jailhouse/commit/fcfa82aa1bcb3bd9186377095635de105eec4d6e
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm64/Makefile
M hypervisor/arch/arm64/entry.S
A hypervisor/arch/arm64/exception.S
A hypervisor/arch/arm64/include/asm/traps.h
A hypervisor/arch/arm64/traps.c
Log Message:
-----------
hypervisor: arm64: initial exception handling and catch EL2 aborts
Catch exceptions on the AArch64 target of Jailhouse. Catch and aborts
from EL2 that might be caused by the hypervisor.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Signed-off-by: Dmitry Voytik <dmitry...@huawei.com>
Commit: ce4db40722f431342aa5f19c5ea45dc9cbcb5d23
https://github.com/siemens/jailhouse/commit/ce4db40722f431342aa5f19c5ea45dc9cbcb5d23
Author: Dmitry Voytik <dmitry...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm64/traps.c
Log Message:
-----------
hypervisor: arm64: dump stack on unhandled exceptions
Dump stack in the following cases:
* exception in EL2. We can determine the stack size
* unhandled exceptions in EL1/0. We can't determine the stack
size thus we just print 512 bytes.
For EL2 exceptions the debug output will be like this:
FATAL: Unhandled HYP exception: synchronous abort from EL2
pc: 00000000fc00469c lr: 00000000fc004688 spsr: 200003c9 EL2
sp: 00000000fc015e30 esr: 25 1 0000044
x0: ffffffff00000000 x1: 0000000000000001 x2: 00000000fc00bd14
x3: ffffff80ffffffc8 x4: 00000000fc010000 x5: 0000000000000004
x6: ffffffc000afe000 x7: 00000000ffffe188 x8: 0000000000005d25
x9: 0000000000000001 x10: ffffffc035766a40 x11: ffffffbdc2d23f80
x12: 0000000000000862 x13: 0000007f92bd7cb0 x14: 0000007f92a67bc8
x15: 0000000000005798 x16: ffffffc0000a2794 x17: 0000000000412288
x18: 0000000000000000 x19: 0000000001930047 x20: 0000000000000004
x21: 0000000000000001 x22: 0000000000000001 x23: 00000000fc015eb8
x24: 00000000000001c0 x25: 0000000000000000 x26: ffffffc000afe6d8
x27: ffffffc035470000 x28: ffffffc034e08000 x29: 00000000fc015e30
Hypervisor stack before exception (0x00000000fc015e30 - 0x00000000fc016000):
5e20: fc015e90 00000000 fc00a298 00000000
5e40: fc015f00 00000000 fc015000 00000000 00559cb8 ffffffc0 00b69000 ffffffc0
5e60: 00b00000 ffffffc0 000001c0 00000000 0000001e 00000000 fc015cf5 00000000
5e80: fc015e90 00000000 0000001e 001e0100 fc015ee0 00000000 fc00a3b0 00000000
5ea0: fc015f00 00000000 fc00b478 00000000 fc015ee0 00000000 fc015f08 00000000
5ec0: 93930047 00000000 200001c5 00000000 00310820 ffffffc0 34e0bbc0 ffffffc0
5ee0: 00000000 00000000 fc009c54 00000000 00040000 00000000 00b00ea0 ffffffc0
5f00: 00000001 00000000 00000f00 ffffff80 00000004 00000000 00000040 00000000
5f20: 00b00ee0 ffffffc0 00559cc0 ffffffc0 00000004 00000000 00afe000 ffffffc0
5f40: ffffe188 00000000 00005d25 00000000 00000001 00000000 35766a40 ffffffc0
5f60: c2d23f80 ffffffbd 00000862 00000000 92bd7cb0 0000007f 92a67bc8 0000007f
5f80: 00005798 00000000 000a2794 ffffffc0 00412288 00000000 00000000 00000000
5fa0: 00040000 00000000 00b00ea0 ffffffc0 00559cb8 ffffffc0 00b69000 ffffffc0
5fc0: 00b00000 ffffffc0 000001c0 00000000 00000000 00000000 00afe6d8 ffffffc0
5fe0: 35470000 ffffffc0 34e08000 ffffffc0 34e0bbc0 ffffffc0 003107fc ffffffc0
6000: 8008a800
Signed-off-by: Dmitry Voytik <dmitry...@huawei.com>
Commit: 2a574d9bd408a694bcaf6531039f75216730f7c1
https://github.com/siemens/jailhouse/commit/2a574d9bd408a694bcaf6531039f75216730f7c1
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A hypervisor/arch/arm64/include/asm/setup.h
M hypervisor/arch/arm64/setup.c
Log Message:
-----------
hypervisor: arm64: plug the hypervisor mmu code
Enable the MMU mappings for the hypervisor running in EL2, and add
functions to map device regions to the hypervisor address space.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 868b6c76f974ba5de8600496fe4f4b8a47827625
https://github.com/siemens/jailhouse/commit/868b6c76f974ba5de8600496fe4f4b8a47827625
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/paging.h
M hypervisor/arch/arm/include/asm/paging_modes.h
M hypervisor/arch/arm/mmu_cell.c
M hypervisor/arch/arm/paging.c
M hypervisor/arch/arm64/entry.S
M hypervisor/arch/arm64/include/asm/paging.h
Log Message:
-----------
hypervisor: arm64: implement support for PA range of up to 48 bits
We currently support 3 levels of page tables for a 39 bits PA range
on ARM. This patch implements support for 4 level page tables on
AArch64, for PA ranges from 40 to 48 bits. This will allow to use
Jailhouse on more targets.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: c1a389264e445af82089126b986300dc41831bef
https://github.com/siemens/jailhouse/commit/c1a389264e445af82089126b986300dc41831bef
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm64/include/asm/traps.h
M hypervisor/arch/arm64/mmio.c
M hypervisor/arch/arm64/traps.c
Log Message:
-----------
hypervisor: arm64: handle accesses to emulated mmio regions
Catch accesses to the mmio regions that we want to handle from the
hypervisor. These are used also by the GIC code.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Signed-off-by: Dmitry Voytik <dmitry...@huawei.com>
Commit: efa5f00fe216756dc103e131211b676725489235
https://github.com/siemens/jailhouse/commit/efa5f00fe216756dc103e131211b676725489235
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm64/Makefile
M hypervisor/arch/arm64/control.c
M hypervisor/arch/arm64/include/asm/cell.h
M hypervisor/arch/arm64/include/asm/percpu.h
M hypervisor/arch/arm64/mmio.c
M hypervisor/arch/arm64/setup.c
M hypervisor/arch/arm64/traps.c
Log Message:
-----------
hypervisor: arm64: plug the irqchip and GICv2 code from AArch32
We plug the irqchip handling code, and the GICv2 implementation from
AArch32.
GICv3 is slightly trickier; it makes heavier use of the sysregs, so
we will need to review more carefully that the sysregs macros do
the right thing.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 4fa46d1b534a49678e024b2c84f2aaad8583e6fb
https://github.com/siemens/jailhouse/commit/4fa46d1b534a49678e024b2c84f2aaad8583e6fb
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/psci.h
M hypervisor/arch/arm/psci.c
M hypervisor/arch/arm64/Makefile
M hypervisor/arch/arm64/control.c
M hypervisor/arch/arm64/include/asm/percpu.h
A hypervisor/arch/arm64/psci_low.S
M hypervisor/arch/arm64/setup.c
M hypervisor/arch/arm64/traps.c
Log Message:
-----------
hypervisor: arm64: PSCI support for SMP on AArch64
On AArch64 we pretty much rely on PSCI being present for SMP
support (turning multiple cores on and off). This patch implements
the helpers needed for SMP and plugs in the PSCI code from AArch32.
On AArch64 PSCI calls can be issued via SVC64 hypercalls as well,
contrary to AArch32 which uses SVC32 calls only. We add the changes
necessary to support the hypercalls that are used by a Linux root
cell. CPU hotplug now is still working after we enable Jailhouse.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: e011a787cb5c95a62e952d57726b08e59b70a20e
https://github.com/siemens/jailhouse/commit/e011a787cb5c95a62e952d57726b08e59b70a20e
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm64/setup.c
Log Message:
-----------
hypervisor: arm64: reanimate the root cell back from the dead
We have now enough implemented functionality to return to the root
cell. We just need to enable guest traps, which will be handled by
the MMU, MMIO, and GIC code we already plugged to the port. Finally,
we restore the state of the root cell that we previously stored in
the stack.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: dac7904a67d246c1b62b27840efdfd376767cd80
https://github.com/siemens/jailhouse/commit/dac7904a67d246c1b62b27840efdfd376767cd80
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm64/traps.c
Log Message:
-----------
hypervisor: arm64: hande hypercalls from the cells
Plug in the core handler for hypercalls, so we can start implementing
the more interesting stuff.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 5dbd24845c74b52d00a5818a0a7ffae080169180
https://github.com/siemens/jailhouse/commit/5dbd24845c74b52d00a5818a0a7ffae080169180
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm64/control.c
M hypervisor/arch/arm64/entry.S
M hypervisor/arch/arm64/include/asm/paging.h
M hypervisor/arch/arm64/include/asm/percpu.h
M hypervisor/arch/arm64/setup.c
M hypervisor/arch/arm64/traps.c
Log Message:
-----------
hypervisor: arm64: hypervisor disable support
Add hypervisor disable support to the Jailhouse firmware. Handle
Jailhouse disable calls from the root cell, and also disable the
hypervisor in case of an error during initialization.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 908e98889d8ff335eead1152e9acfb8b9606a32e
https://github.com/siemens/jailhouse/commit/908e98889d8ff335eead1152e9acfb8b9606a32e
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm64/control.c
M hypervisor/arch/arm64/include/asm/cell.h
Log Message:
-----------
hypervisor: arm64: implement cell control infrastructure
This patch mostly implements the functionality needed to create
and control new cells. The functionality is very similar to the
one from AArch32, and there is potential to unify some code in
the future between the architectures.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: b7fb3d078a3b37b2cf74043f77fc5fb32063d4f2
https://github.com/siemens/jailhouse/commit/b7fb3d078a3b37b2cf74043f77fc5fb32063d4f2
Author: Dmitry Voytik <dmitry...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A scripts/arm64-parsedump.py
Log Message:
-----------
tools: arm64: add exception dump parser tool
Add ./scripts/arm64-parsedump.py tool. This tool decodes an ARM64
exception dump and prints human-readable stack trace like this:
[0x00000000fc008688] arch_handle_dabt mmio.c:97
[0x00000000fc009acc] arch_handle_trap traps.c:143
The tool can read dumps from files (passed via -f parameter)
or from stdin stream (which could be also piped-in).
Signed-off-by: Dmitry Voytik <dmitry...@huawei.com>
Commit: bfedd3d072628420ce10928f2a828e59194a6dd6
https://github.com/siemens/jailhouse/commit/bfedd3d072628420ce10928f2a828e59194a6dd6
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M inmates/lib/cmdline.c
Log Message:
-----------
inmates: lib: fix command line parsing of hex ints
The cmdline_parse_int function is currently broken;
luckily, it is a simple fix.
Commit: 67792e2e3259c6da454d5921c11d33f80da26b1d
https://github.com/siemens/jailhouse/commit/67792e2e3259c6da454d5921c11d33f80da26b1d
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M inmates/demos/arm/uart-demo.c
M inmates/lib/arm/include/inmate.h
Log Message:
-----------
inmates: arm: uart-demo: move heartbeat to header file
Moving the heartbeat function to a header file, so we can reuse
the uart-demo just by reimplementing the heartbeat on AArch64.
Commit: 67b3c20e8ee4463a361289cd6cdebf75b85a5acc
https://github.com/siemens/jailhouse/commit/67b3c20e8ee4463a361289cd6cdebf75b85a5acc
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M inmates/lib/arm/gic.c
M inmates/lib/arm/include/gic.h
Log Message:
-----------
inmates: arm: lib: move IRQ stack initialization
On AArch64 we won't need to initialize an IRQ stack; just move
the functionality to a header, so we may reuse the gic library.
Commit: 7f893d47da7414045ec8fe96bcd98ab68081f2c5
https://github.com/siemens/jailhouse/commit/7f893d47da7414045ec8fe96bcd98ab68081f2c5
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/sysregs.h
M inmates/lib/arm/timer.c
Log Message:
-----------
inmates, hypervisor: arm: prep timer library for AArch64
This patch is a minor touch up, that will allow to build the
ARM timer inmate library also on AArch64. We just need to add
the EL0 prefix to the CNTFRQ and CNTPCT sysregs, so we can
access them with the same code.
Commit: a996a83cd75d4ac19b3d7910fa43e2d109cd33ae
https://github.com/siemens/jailhouse/commit/a996a83cd75d4ac19b3d7910fa43e2d109cd33ae
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M inmates/Makefile
M inmates/demos/arm64/Makefile
M inmates/lib/arm64/Makefile
A inmates/lib/arm64/Makefile.lib
A inmates/lib/arm64/header.S
A inmates/lib/arm64/include/gic.h
A inmates/lib/arm64/include/inmate.h
A inmates/lib/arm64/include/mach-amd-seattle/mach/gic_v2.h
A inmates/lib/arm64/include/mach-amd-seattle/mach/timer.h
A inmates/lib/arm64/include/mach-amd-seattle/mach/uart.h
A inmates/lib/arm64/include/mach-foundation-v8/mach/gic_v2.h
A inmates/lib/arm64/include/mach-foundation-v8/mach/timer.h
A inmates/lib/arm64/include/mach-foundation-v8/mach/uart.h
A inmates/lib/arm64/inmate.lds
Log Message:
-----------
inmates: arm64: port imate demos from AArch32 to AArch64
This is a straight port of the inmate demos from AArch32 to AArch64.
These can now be loaded as cells onto a Foundation ARMv8 model.
Code reuse can possible be increased here as well.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: c28e1cb18e4010bd26ca90c99bf10fbabaac1007
https://github.com/siemens/jailhouse/commit/c28e1cb18e4010bd26ca90c99bf10fbabaac1007
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/irqchip.h
Log Message:
-----------
hypervisor: arm64: add work around for large SPIs on AMD Seattle
The AMD Seattle board features SPI ids that are larger than 64,
which we do not support properly. This workaround allows us to
demonstrate working cells on this target, until we have a proper fix.
This implies that only specific setups will be used on the
AMD Seattle; the IRQs for the uart and the second xgmac are being
passed to the cells.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: d979ea998afce4dbf769cdedaa684ac3d91f20d5
https://github.com/siemens/jailhouse/commit/d979ea998afce4dbf769cdedaa684ac3d91f20d5
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A configs/foundation-v8-uart-demo.c
Log Message:
-----------
hypervisor: arm64: add uart demo cell config for Foundation v8
Add a cell configuration file for the foundation-v8 model, to
be used with the PL011 UART inmate demo.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 4eabd8de9a6b8f5dada277bf4ed1f338bf1e76ea
https://github.com/siemens/jailhouse/commit/4eabd8de9a6b8f5dada277bf4ed1f338bf1e76ea
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A configs/foundation-v8-gic-demo.c
Log Message:
-----------
hypervisor: arm64: gic inmate cell config for foundation-v8
Add a cell configuration file for the gic inmate demo, for the
foundation-v8 model.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 9dd4225c6fbf041e0d42e1c49f15125528b849fe
https://github.com/siemens/jailhouse/commit/9dd4225c6fbf041e0d42e1c49f15125528b849fe
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A configs/amd-seattle-uart-demo.c
Log Message:
-----------
hypervisor: arm64: UART demo cell config for the AMD Seattle
Add a cell configuration file for the AMD Seattle development
board, to be used with the PL011 UART demo inmate.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 6a67e73b63a6bb4be7d31041f85f37c3af70c346
https://github.com/siemens/jailhouse/commit/6a67e73b63a6bb4be7d31041f85f37c3af70c346
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A configs/amd-seattle-gic-demo.c
Log Message:
-----------
hypervisor: arm64: gic demo cell config for the AMD Seattle
Add a cell configuration file to use on the AMD Seattle, to be
used with the gic demo inmate.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 104a53135912dae65f89bcaf4b7023ee399bd0ad
https://github.com/siemens/jailhouse/commit/104a53135912dae65f89bcaf4b7023ee399bd0ad
Author: Dmitry Voytik <dmitry...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M inmates/tools/arm64/Makefile
A inmates/tools/arm64/linux-loader.c
Log Message:
-----------
inmates: arm64: implement non-root linux loader
This patch implements a loader, that can be used to boot a Linux
kernel in a Jailhouse cell on AArch64.
Signed-off-by: Dmitry Voytik <dmitry...@huawei.com>
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
[antonios...@huawei.com:
- split foundation-v8 configuration to a separate patch
- small fixes in the linux loader output
- take kernel and dtb address using cell load command line ]
Commit: 1b516365e0b909dd55290e3f316c3421e5964fb5
https://github.com/siemens/jailhouse/commit/1b516365e0b909dd55290e3f316c3421e5964fb5
Author: Dmitry Voytik <dmitry...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A configs/foundation-v8-linux-demo.c
A samples/kernel-inmate-foundation-v8.dts
Log Message:
-----------
hypervisor: arm64: add linux inmate cell config for foundation-v8
Add the cell configuration files, and some helper scripts and device
tree for the foundation-v8 model. These can be used to load a linux
inmate on a cell on that target.
Signed-off-by: Dmitry Voytik <dmitry...@huawei.com>
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
[antonios...@huawei.com: split off as a separate patch,
some minor renaming for consistency]
Commit: 005430841176355e078d0e6715053b4690be7c54
https://github.com/siemens/jailhouse/commit/005430841176355e078d0e6715053b4690be7c54
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A configs/amd-seattle-linux-demo.c
A samples/kernel-inmate-amd-seattle.dts
Log Message:
-----------
hypervisor: arm64: add linux inmate cell config for AMD Seattle
Add the cell configuration files, and some helper scripts and device
tree for the AMD Seattle development board. These can be used to
load a linux inmate on a cell on that target.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 3486e6fe28dffb6e7ec976ef6d8d00e07f4c37d2
https://github.com/siemens/jailhouse/commit/3486e6fe28dffb6e7ec976ef6d8d00e07f4c37d2
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M .travis.yml
M ci/build-all-configs.sh
M ci/gen-kernel-build.sh
A ci/kernel-config-amd-seattle
Log Message:
-----------
ci: Add support for arm64
This adds arm64 to CI via the AMD Seattle configuration.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: eaab4ce51fe1f68ae2f8666096a5a5fc48b7f087
https://github.com/siemens/jailhouse/commit/eaab4ce51fe1f68ae2f8666096a5a5fc48b7f087
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M driver/main.c
M hypervisor/hypervisor.lds.S
M hypervisor/include/jailhouse/header.h
M hypervisor/setup.c
Log Message:
-----------
core, driver: Pass rounded-up core size in hypervisor header
Hypervisor and root kernel may have different ideas about PAGE_SIZE.
This will cause wrong hypervisor core size calculations as seen on arm64
with 64K Linux PAGE_SIZE.
Avoid this trap by moving the round-up into the hypervisor code, passing
a ready-to-be-used size value in the header.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Compare: https://github.com/siemens/jailhouse/compare/06ab4106999c...eaab4ce51fe1
Home: https://github.com/siemens/jailhouse
Commit: 6454087832d4d9e9fbe989f533e5f8a91a717809
https://github.com/siemens/jailhouse/commit/6454087832d4d9e9fbe989f533e5f8a91a717809
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M driver/main.c
M hypervisor/arch/arm/include/asm/jailhouse_hypercall.h
M hypervisor/arch/x86/include/asm/jailhouse_hypercall.h
M hypervisor/setup.c
Log Message:
-----------
driver: ioremap the hypervisor firmware to any kernel address
At the moment the Linux driver maps the Jailhouse binary to
JAILHOUSE_BASE. The underlying assumption is that Linux may map the
firmware (in the Linux kernel space), to the same virtual address it
has been built to run from.
This assumption is unworkable on ARMv8 processors running in AArch64
mode. Kernel memory is allocated in a high address region, that is
not addressable from EL2, where the hypervisor will run from.
This patch removes the assumption, by introducing the
JAILHOUSE_BORROW_ROOT_PT define, which describes the behavior of the
current architectures.
We also turn the entry point in the header, into an offset from the
Jailhouse load address, so we can enter the image regardless of
where it will be mapped.
On AArch64, JAILHOUSE_BASE will be the physical address the
hypervisor will be loaded to. This way, Jailhouse will run with
identity mapping in EL2. The Linux driver sets the address to the
debug UART accordingly.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: acea65443ab0c4fbdc44696c6faea79b8a45e3a4
https://github.com/siemens/jailhouse/commit/acea65443ab0c4fbdc44696c6faea79b8a45e3a4
Author: Dmitry Voytik <dmitry...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M driver/cell.c
M driver/main.c
Log Message:
-----------
driver: sync I-cache, D-cache and memory
Syncronize I-cache with D-cache after loading the hypervisor
image or a cell image. This must be done in arm64 according to
ARMv8 ARM spec. See page 1712, D3.4.6 "Non-cacheable accesses
and instruction caches".
This patch fixes coherency problems observed on real HW targets.
On x86 this operation is a NOP.
Signed-off-by: Dmitry Voytik <dmitry...@huawei.com>
Commit: ea171ff353fbdecc66b28089af98d10c11d2983b
https://github.com/siemens/jailhouse/commit/ea171ff353fbdecc66b28089af98d10c11d2983b
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/paging.h
M hypervisor/arch/arm/irqchip.c
M hypervisor/arch/arm/mmu_cell.c
M hypervisor/arch/x86/apic.c
M hypervisor/arch/x86/include/asm/paging.h
M hypervisor/arch/x86/ioapic.c
M hypervisor/arch/x86/svm.c
M hypervisor/arch/x86/vmx.c
M hypervisor/arch/x86/vtd.c
M hypervisor/control.c
M hypervisor/include/jailhouse/paging.h
M hypervisor/mmio.c
M hypervisor/paging.c
M hypervisor/pci.c
M hypervisor/pci_ivshmem.c
Log Message:
-----------
core: reimplement page_alloc to allow aligned allocations
The function page_alloc allows us to allocate any number of
pages, however they will always be aligned on page boundaries.
The new page_alloc implementation takes an extra bool align
parameter, which allows us to allocate N pages that will be
aligned by N * PAGE_SIZE. N needs to be a power of two.
This will be used on the AArch64 port of Jailhouse to support
physical address ranges from 40 to 44 bits: in these
configurations, the initial page table level may take up
multiple consecutive pages.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 98283eebd6b46fa64b7a1e68465e54bdb65cdad2
https://github.com/siemens/jailhouse/commit/98283eebd6b46fa64b7a1e68465e54bdb65cdad2
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/irqchip.h
Log Message:
-----------
hypervisor: arm: pass SPIs with large ids to the root cell
The current design for cell configuration files, defines the SPIs
to be passed to a cell as 64 bit bitmap. In order to use Jailhouse
on targets that have SPI ids larger than 64, we need to work
around this limitation.
Pass large SPIs to the root cell for now. A permanent solution to
this problem will need to tackle the cell configuration format.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 6286f3b676639d1692e8668acbc0c4ac92111cd1
https://github.com/siemens/jailhouse/commit/6286f3b676639d1692e8668acbc0c4ac92111cd1
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm/lib.c
Log Message:
-----------
hypervisor: arm: phys_processor_id should return logical id
Currently the function phys_processor_id identifies the current
CPU by reading the MPIDR register. However, on systems with
multiple implemented affinity levels, the scheme used by this
register is hierarchical and does not correspond to the logical
IDs allocated to CPUs.
Change phys_processor_id to return the logical CPU id, so we
don't run into problems when we start implementing support for
affinity levels.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 40b4cc1e492f9638c6de211c728f96824c40f264
https://github.com/siemens/jailhouse/commit/40b4cc1e492f9638c6de211c728f96824c40f264
Author: Claudio Fontana <claudio...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm/lib.c
M hypervisor/lib.c
Log Message:
-----------
core: lib: move memcpy implementation from the ARM port
Move the memcpy implementation from the ARM port,
to the core library.
Signed-off-by: Claudio Fontana <claudio...@huawei.com>
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
[antonios...@huawei.com: removed all signs of weakness!]
Commit: c71954152339663698dea2394e976aa67d6bdec2
https://github.com/siemens/jailhouse/commit/c71954152339663698dea2394e976aa67d6bdec2
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm/control.c
M hypervisor/arch/arm/lib.c
Log Message:
-----------
hypervisor: arm: move arm_cpu_virt2phys to lib.c
Putting arm_cpu_virt2phys under arch/arm/lib.c is a little
more consistent (it can become friends with phys_processor_id),
and we'll benefit by sharing the implementation with AArch64.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: cc8ee2b83c4b1f71aac50d5637d89116cf91e1c2
https://github.com/siemens/jailhouse/commit/cc8ee2b83c4b1f71aac50d5637d89116cf91e1c2
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/control.h
M hypervisor/arch/arm/include/asm/percpu.h
M hypervisor/arch/arm/lib.c
M hypervisor/arch/arm/psci.c
M hypervisor/arch/arm/setup.c
Log Message:
-----------
hypervisor: arm: psci: support multiple affinity levels in MPIDR
PSCI actually takes CPU parameters by the MPIDR id, which may
differ from the logical id of the CPU. This patch is the first step
into properly handling the CPU affinity levels in the MPIDR.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 942c4063eae4be3644bfa3bff9e196a32dcbdab9
https://github.com/siemens/jailhouse/commit/942c4063eae4be3644bfa3bff9e196a32dcbdab9
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/psci.h
Log Message:
-----------
hypervisor: arm: make IS_PSCI_FN macro more restrictive
The previous version of the macro allows for more false positives
than necessary.
The SVC32 and SVC64 versions of the PSCI function ids differ only
on one bit. Mask this bit from the function id prefix and compare.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 6761af3953ede05e3bc86e6c2dab56f439e4b9e4
https://github.com/siemens/jailhouse/commit/6761af3953ede05e3bc86e6c2dab56f439e4b9e4
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/processor.h
M hypervisor/arch/arm/mmu_cell.c
Log Message:
-----------
hypervisor: arm: hide TLB flush behind a macro
Hide TLB flushes issues by the MMU code behind a macro, so we can
increase our chances of reusing some of this code.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 04ed1c18f11541fef7482c0979c92b75f9c6ee94
https://github.com/siemens/jailhouse/commit/04ed1c18f11541fef7482c0979c92b75f9c6ee94
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/paging.h
M hypervisor/arch/arm/mmu_cell.c
Log Message:
-----------
hypervisor: arm: put the value of VTCR for cells in a define
We can reuse the code under hypervisor/arch/arm/mmu_cell.c for the
AArch64 port, save for the value we use for the VTCRL. AArch64 will
need in addition to the flags set by the AArch32 port, to set the
size of the address space to 40 bits; at least initially, until we
implement the new MMU features in ARMv8.
We put this behind a define in asm/paging.h to allow this reuse.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: f2e5bb1f6ea4f9dcc343776cdf444bc4d5c0ae62
https://github.com/siemens/jailhouse/commit/f2e5bb1f6ea4f9dcc343776cdf444bc4d5c0ae62
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A hypervisor/arch/arm64/include/asm/sysregs.h
Log Message:
-----------
hypervisor: arm64: add sysregs helper macros
On the AArch32 port of Jailhouse, the arm_write_sysreg and
arm_read_sysreg macros are used to access the system registers.
Implementing these helpers on AArch64 allows to approach some low
hanging fruit when looking for code to reuse from the AArch32 port.
On AArch64 we always get a u64 value from a system register, while
on AArch32 it might be either u32 or u64. We need to look at the
users of this macro on a case by case basis and see if it makes
sense to reuse code.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 856c33d1c2464aee8ad6d16dea0cf40b1e7b6cdf
https://github.com/siemens/jailhouse/commit/856c33d1c2464aee8ad6d16dea0cf40b1e7b6cdf
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A hypervisor/arch/arm64/include/asm/processor.h
Log Message:
-----------
hypervisor: arm64: add asm/processor.h header for AArch64
Add an initial asm/processor.h header for AArch64. This header is
loosely based on the version for AArch32, but we have kept the stuff
that we use.
More correctness checking still needs to be done.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 8331a206780dcdc86fd6c906f2d12b04e156e4e4
https://github.com/siemens/jailhouse/commit/8331a206780dcdc86fd6c906f2d12b04e156e4e4
Author: Dmitry Voytik <dmitry...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A hypervisor/arch/arm64/include/asm/control.h
Log Message:
-----------
hypervisor: arm64: add control.h header file
Add the header file control.h to the AArch64 port of Jailhouse.
Signed-off-by: Dmitry Voytik <dmitry...@huawei.com>
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
[antonios...@huawei.com: split off as a separate patch]
Commit: 3a38f6e5f88534ef089e908108ab6c0be9766a7c
https://github.com/siemens/jailhouse/commit/3a38f6e5f88534ef089e908108ab6c0be9766a7c
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A hypervisor/arch/arm64/include/asm/paging.h
Log Message:
-----------
hypervisor: arm64: add definitions for the AArch64 page table format
The AArch64 page table format is very similar, almost identical to
the AArch32 page table format. Add a header file for the AArch64 page
table format, based on the AArch32 implementation.
AArch64 introduces an extra level of page tables, for a total of
four, and support for different translation granule sizes. Disabling
the level zero of the page tables, and using a granule size of 4Kb,
results in an identical page table format with AArch32. With these
parameters, we can address 39 bits of memory.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 24ddab5f9db6a6d6d5330158d39e24494bdb17f0
https://github.com/siemens/jailhouse/commit/24ddab5f9db6a6d6d5330158d39e24494bdb17f0
Author: Dmitry Voytik <dmitry...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A hypervisor/arch/arm64/include/asm/types.h
Log Message:
-----------
hypervisor: arm64: add types.h
Add the asm/types.h header file, which defines the size of the data
types.
Signed-off-by: Dmitry Voytik <dmitry...@huawei.com>
Commit: c5e85c28b814e45fd6686589059c31cdfc5932e9
https://github.com/siemens/jailhouse/commit/c5e85c28b814e45fd6686589059c31cdfc5932e9
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A hypervisor/arch/arm64/include/asm/spinlock.h
Log Message:
-----------
hypervisor: arm64: spinlock implementation
Implement spinlocks for the hypervisor firmware, on AArch64.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 368d3bde2d0b858e6b15e329d01429bacddaec39
https://github.com/siemens/jailhouse/commit/368d3bde2d0b858e6b15e329d01429bacddaec39
Author: Claudio Fontana <claudio...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A hypervisor/arch/arm64/include/asm/bitops.h
Log Message:
-----------
arm64: implement bitops
implement set_bit, clear_bit, test_and_set_bit.
test_and_set_bit is used only in the panic_printk apparently,
while set_bit and clear_bit are used in page table handling code.
Signed-off-by: Claudio Fontana <claudio...@huawei.com>
Commit: d5c2fa9d56a89a47f85e8411dd1db4989f0b6e35
https://github.com/siemens/jailhouse/commit/d5c2fa9d56a89a47f85e8411dd1db4989f0b6e35
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A hypervisor/arch/arm64/include/asm/percpu.h
Log Message:
-----------
hypervisor: arm64: add percpu.h header file
Add the percpu.h header file for the AArch64 implementation. This is
the bare bones version of the header needed to compile a stub
hypervisor binary on AArch64. A lot of these fields could probably
be moved to an arch independent header.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: c823d30ee16e629932c7e94bff0c615e66512c01
https://github.com/siemens/jailhouse/commit/c823d30ee16e629932c7e94bff0c615e66512c01
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A hypervisor/arch/arm64/include/asm/cell.h
Log Message:
-----------
hypervisor: arm64: add cell.h header file
Add the initial cell.h header file needed to build on AArch64.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: e8161dc14826432c1811f3964933e2de3045d367
https://github.com/siemens/jailhouse/commit/e8161dc14826432c1811f3964933e2de3045d367
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A hypervisor/arch/arm64/include/asm/jailhouse_hypercall.h
Log Message:
-----------
hypervisor: arm64: add jailhouse_hypercall.h header file
Add the jailhouse_hypercall.h header file for AArch64. We will need
this also from the Linux side, in order to load Jailhouse in memory
and to issue hypercalls to an already loaded instance of the
hypervisor.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 8d2700d2418e3364f4c3c8c10111dd42255aac5c
https://github.com/siemens/jailhouse/commit/8d2700d2418e3364f4c3c8c10111dd42255aac5c
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/Makefile
A hypervisor/arch/arm64/Makefile
A hypervisor/arch/arm64/asm-defines.c
A hypervisor/arch/arm64/control.c
A hypervisor/arch/arm64/entry.S
M hypervisor/arch/arm64/include/asm/control.h
A hypervisor/arch/arm64/include/asm/head.h
M hypervisor/arch/arm64/include/asm/percpu.h
A hypervisor/arch/arm64/include/asm/platform.h
A hypervisor/arch/arm64/mmio.c
A hypervisor/arch/arm64/setup.c
A inmates/demos/arm64/Makefile
A inmates/lib/arm64/Makefile
A inmates/tools/arm64/Makefile
Log Message:
-----------
hypervisor: arm64: minimum stubs to allow building on AArch64
Add the minimum stub functions expected by the rest of the codebase
to enable building on AArch64. We may implement the missing AArch64
functionality from here.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 1b53808f991649609e5d682f528a0d60db92a0c1
https://github.com/siemens/jailhouse/commit/1b53808f991649609e5d682f528a0d60db92a0c1
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A configs/foundation-v8.c
M hypervisor/arch/arm64/include/asm/platform.h
Log Message:
-----------
core: add root cell configuration for the ARMv8 Foundation model
Add under config/foundation-v8.c a root cell configuration for the
ARMv8 Foundation model, so we can in use this target with Jailhouse.
We also add the neccessary parameters in asm/platform.h for this
model.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: ad763f7de20ea3a50b18470d24b6da1338cb9990
https://github.com/siemens/jailhouse/commit/ad763f7de20ea3a50b18470d24b6da1338cb9990
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A ci/jailhouse-config-amd-seattle.h
A configs/amd-seattle.c
M hypervisor/arch/arm/include/asm/uart_pl011.h
M hypervisor/arch/arm64/include/asm/platform.h
Log Message:
-----------
hypervisor: arm64: root cell configuration for the AMD Seattle
Add the root cell configuration and necessary headers to build
and run Jailhouse on the AMD Seattle development board.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 8c1acac3f02d7b71df7f1616416f68d0e948b4b5
https://github.com/siemens/jailhouse/commit/8c1acac3f02d7b71df7f1616416f68d0e948b4b5
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm64/entry.S
M hypervisor/arch/arm64/include/asm/percpu.h
Log Message:
-----------
hypervisor: arm64: implement entry code to the hypervisor firmware
Implement the entry point we will jump to after the Linux driver
loads the firmware to memory. Here we also set up a stack for the
hypervisor to use.
Unlike AArch32, we jump to EL2 as soon as we enter the hypervisor
binary.
To do this, we also set up temporary MMU mappings. We use just two
pages, to statically configure the MMU for identity mapping;
we need this in order to perform unaligned accesses from the
hypervisor binary during early initialization.
To generate the early page tables at build time, we need to know the
Jailhouse physical address, and the physical address of the debug
UART. We introduce this change of behaviour in AArch64, because in
this architecture we do not have the option of using the page tables
set up previously by Linux.
Reviewed for cache coherency correctness by Dmitry Voytik.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Signed-off-by: Dmitry Voytik <dmitry...@huawei.com>
Commit: fcfa82aa1bcb3bd9186377095635de105eec4d6e
https://github.com/siemens/jailhouse/commit/fcfa82aa1bcb3bd9186377095635de105eec4d6e
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm64/Makefile
M hypervisor/arch/arm64/entry.S
A hypervisor/arch/arm64/exception.S
A hypervisor/arch/arm64/include/asm/traps.h
A hypervisor/arch/arm64/traps.c
Log Message:
-----------
hypervisor: arm64: initial exception handling and catch EL2 aborts
Catch exceptions on the AArch64 target of Jailhouse. Catch and aborts
from EL2 that might be caused by the hypervisor.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Signed-off-by: Dmitry Voytik <dmitry...@huawei.com>
Commit: ce4db40722f431342aa5f19c5ea45dc9cbcb5d23
https://github.com/siemens/jailhouse/commit/ce4db40722f431342aa5f19c5ea45dc9cbcb5d23
Author: Dmitry Voytik <dmitry...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm64/traps.c
Log Message:
-----------
hypervisor: arm64: dump stack on unhandled exceptions
Dump stack in the following cases:
* exception in EL2. We can determine the stack size
* unhandled exceptions in EL1/0. We can't determine the stack
size thus we just print 512 bytes.
For EL2 exceptions the debug output will be like this:
FATAL: Unhandled HYP exception: synchronous abort from EL2
pc: 00000000fc00469c lr: 00000000fc004688 spsr: 200003c9 EL2
sp: 00000000fc015e30 esr: 25 1 0000044
x0: ffffffff00000000 x1: 0000000000000001 x2: 00000000fc00bd14
x3: ffffff80ffffffc8 x4: 00000000fc010000 x5: 0000000000000004
x6: ffffffc000afe000 x7: 00000000ffffe188 x8: 0000000000005d25
x9: 0000000000000001 x10: ffffffc035766a40 x11: ffffffbdc2d23f80
x12: 0000000000000862 x13: 0000007f92bd7cb0 x14: 0000007f92a67bc8
x15: 0000000000005798 x16: ffffffc0000a2794 x17: 0000000000412288
x18: 0000000000000000 x19: 0000000001930047 x20: 0000000000000004
x21: 0000000000000001 x22: 0000000000000001 x23: 00000000fc015eb8
x24: 00000000000001c0 x25: 0000000000000000 x26: ffffffc000afe6d8
x27: ffffffc035470000 x28: ffffffc034e08000 x29: 00000000fc015e30
Hypervisor stack before exception (0x00000000fc015e30 - 0x00000000fc016000):
5e20: fc015e90 00000000 fc00a298 00000000
5e40: fc015f00 00000000 fc015000 00000000 00559cb8 ffffffc0 00b69000 ffffffc0
5e60: 00b00000 ffffffc0 000001c0 00000000 0000001e 00000000 fc015cf5 00000000
5e80: fc015e90 00000000 0000001e 001e0100 fc015ee0 00000000 fc00a3b0 00000000
5ea0: fc015f00 00000000 fc00b478 00000000 fc015ee0 00000000 fc015f08 00000000
5ec0: 93930047 00000000 200001c5 00000000 00310820 ffffffc0 34e0bbc0 ffffffc0
5ee0: 00000000 00000000 fc009c54 00000000 00040000 00000000 00b00ea0 ffffffc0
5f00: 00000001 00000000 00000f00 ffffff80 00000004 00000000 00000040 00000000
5f20: 00b00ee0 ffffffc0 00559cc0 ffffffc0 00000004 00000000 00afe000 ffffffc0
5f40: ffffe188 00000000 00005d25 00000000 00000001 00000000 35766a40 ffffffc0
5f60: c2d23f80 ffffffbd 00000862 00000000 92bd7cb0 0000007f 92a67bc8 0000007f
5f80: 00005798 00000000 000a2794 ffffffc0 00412288 00000000 00000000 00000000
5fa0: 00040000 00000000 00b00ea0 ffffffc0 00559cb8 ffffffc0 00b69000 ffffffc0
5fc0: 00b00000 ffffffc0 000001c0 00000000 00000000 00000000 00afe6d8 ffffffc0
5fe0: 35470000 ffffffc0 34e08000 ffffffc0 34e0bbc0 ffffffc0 003107fc ffffffc0
6000: 8008a800
Signed-off-by: Dmitry Voytik <dmitry...@huawei.com>
Commit: 2a574d9bd408a694bcaf6531039f75216730f7c1
https://github.com/siemens/jailhouse/commit/2a574d9bd408a694bcaf6531039f75216730f7c1
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A hypervisor/arch/arm64/include/asm/setup.h
M hypervisor/arch/arm64/setup.c
Log Message:
-----------
hypervisor: arm64: plug the hypervisor mmu code
Enable the MMU mappings for the hypervisor running in EL2, and add
functions to map device regions to the hypervisor address space.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 868b6c76f974ba5de8600496fe4f4b8a47827625
https://github.com/siemens/jailhouse/commit/868b6c76f974ba5de8600496fe4f4b8a47827625
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/paging.h
M hypervisor/arch/arm/include/asm/paging_modes.h
M hypervisor/arch/arm/mmu_cell.c
M hypervisor/arch/arm/paging.c
M hypervisor/arch/arm64/entry.S
M hypervisor/arch/arm64/include/asm/paging.h
Log Message:
-----------
hypervisor: arm64: implement support for PA range of up to 48 bits
We currently support 3 levels of page tables for a 39 bits PA range
on ARM. This patch implements support for 4 level page tables on
AArch64, for PA ranges from 40 to 48 bits. This will allow to use
Jailhouse on more targets.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: c1a389264e445af82089126b986300dc41831bef
https://github.com/siemens/jailhouse/commit/c1a389264e445af82089126b986300dc41831bef
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm64/include/asm/traps.h
M hypervisor/arch/arm64/mmio.c
M hypervisor/arch/arm64/traps.c
Log Message:
-----------
hypervisor: arm64: handle accesses to emulated mmio regions
Catch accesses to the mmio regions that we want to handle from the
hypervisor. These are used also by the GIC code.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Signed-off-by: Dmitry Voytik <dmitry...@huawei.com>
Commit: efa5f00fe216756dc103e131211b676725489235
https://github.com/siemens/jailhouse/commit/efa5f00fe216756dc103e131211b676725489235
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm64/Makefile
M hypervisor/arch/arm64/control.c
M hypervisor/arch/arm64/include/asm/cell.h
M hypervisor/arch/arm64/include/asm/percpu.h
M hypervisor/arch/arm64/mmio.c
M hypervisor/arch/arm64/setup.c
M hypervisor/arch/arm64/traps.c
Log Message:
-----------
hypervisor: arm64: plug the irqchip and GICv2 code from AArch32
We plug the irqchip handling code, and the GICv2 implementation from
AArch32.
GICv3 is slightly trickier; it makes heavier use of the sysregs, so
we will need to review more carefully that the sysregs macros do
the right thing.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 4fa46d1b534a49678e024b2c84f2aaad8583e6fb
https://github.com/siemens/jailhouse/commit/4fa46d1b534a49678e024b2c84f2aaad8583e6fb
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/psci.h
M hypervisor/arch/arm/psci.c
M hypervisor/arch/arm64/Makefile
M hypervisor/arch/arm64/control.c
M hypervisor/arch/arm64/include/asm/percpu.h
A hypervisor/arch/arm64/psci_low.S
M hypervisor/arch/arm64/setup.c
M hypervisor/arch/arm64/traps.c
Log Message:
-----------
hypervisor: arm64: PSCI support for SMP on AArch64
On AArch64 we pretty much rely on PSCI being present for SMP
support (turning multiple cores on and off). This patch implements
the helpers needed for SMP and plugs in the PSCI code from AArch32.
On AArch64 PSCI calls can be issued via SVC64 hypercalls as well,
contrary to AArch32 which uses SVC32 calls only. We add the changes
necessary to support the hypercalls that are used by a Linux root
cell. CPU hotplug now is still working after we enable Jailhouse.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: e011a787cb5c95a62e952d57726b08e59b70a20e
https://github.com/siemens/jailhouse/commit/e011a787cb5c95a62e952d57726b08e59b70a20e
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm64/setup.c
Log Message:
-----------
hypervisor: arm64: reanimate the root cell back from the dead
We have now enough implemented functionality to return to the root
cell. We just need to enable guest traps, which will be handled by
the MMU, MMIO, and GIC code we already plugged to the port. Finally,
we restore the state of the root cell that we previously stored in
the stack.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: dac7904a67d246c1b62b27840efdfd376767cd80
https://github.com/siemens/jailhouse/commit/dac7904a67d246c1b62b27840efdfd376767cd80
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm64/traps.c
Log Message:
-----------
hypervisor: arm64: hande hypercalls from the cells
Plug in the core handler for hypercalls, so we can start implementing
the more interesting stuff.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 5dbd24845c74b52d00a5818a0a7ffae080169180
https://github.com/siemens/jailhouse/commit/5dbd24845c74b52d00a5818a0a7ffae080169180
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm64/control.c
M hypervisor/arch/arm64/entry.S
M hypervisor/arch/arm64/include/asm/paging.h
M hypervisor/arch/arm64/include/asm/percpu.h
M hypervisor/arch/arm64/setup.c
M hypervisor/arch/arm64/traps.c
Log Message:
-----------
hypervisor: arm64: hypervisor disable support
Add hypervisor disable support to the Jailhouse firmware. Handle
Jailhouse disable calls from the root cell, and also disable the
hypervisor in case of an error during initialization.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 908e98889d8ff335eead1152e9acfb8b9606a32e
https://github.com/siemens/jailhouse/commit/908e98889d8ff335eead1152e9acfb8b9606a32e
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm64/control.c
M hypervisor/arch/arm64/include/asm/cell.h
Log Message:
-----------
hypervisor: arm64: implement cell control infrastructure
This patch mostly implements the functionality needed to create
and control new cells. The functionality is very similar to the
one from AArch32, and there is potential to unify some code in
the future between the architectures.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: b7fb3d078a3b37b2cf74043f77fc5fb32063d4f2
https://github.com/siemens/jailhouse/commit/b7fb3d078a3b37b2cf74043f77fc5fb32063d4f2
Author: Dmitry Voytik <dmitry...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A scripts/arm64-parsedump.py
Log Message:
-----------
tools: arm64: add exception dump parser tool
Add ./scripts/arm64-parsedump.py tool. This tool decodes an ARM64
exception dump and prints human-readable stack trace like this:
[0x00000000fc008688] arch_handle_dabt mmio.c:97
[0x00000000fc009acc] arch_handle_trap traps.c:143
The tool can read dumps from files (passed via -f parameter)
or from stdin stream (which could be also piped-in).
Signed-off-by: Dmitry Voytik <dmitry...@huawei.com>
Commit: bfedd3d072628420ce10928f2a828e59194a6dd6
https://github.com/siemens/jailhouse/commit/bfedd3d072628420ce10928f2a828e59194a6dd6
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M inmates/lib/cmdline.c
Log Message:
-----------
inmates: lib: fix command line parsing of hex ints
The cmdline_parse_int function is currently broken;
luckily, it is a simple fix.
Commit: 67792e2e3259c6da454d5921c11d33f80da26b1d
https://github.com/siemens/jailhouse/commit/67792e2e3259c6da454d5921c11d33f80da26b1d
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M inmates/demos/arm/uart-demo.c
M inmates/lib/arm/include/inmate.h
Log Message:
-----------
inmates: arm: uart-demo: move heartbeat to header file
Moving the heartbeat function to a header file, so we can reuse
the uart-demo just by reimplementing the heartbeat on AArch64.
Commit: 67b3c20e8ee4463a361289cd6cdebf75b85a5acc
https://github.com/siemens/jailhouse/commit/67b3c20e8ee4463a361289cd6cdebf75b85a5acc
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M inmates/lib/arm/gic.c
M inmates/lib/arm/include/gic.h
Log Message:
-----------
inmates: arm: lib: move IRQ stack initialization
On AArch64 we won't need to initialize an IRQ stack; just move
the functionality to a header, so we may reuse the gic library.
Commit: 7f893d47da7414045ec8fe96bcd98ab68081f2c5
https://github.com/siemens/jailhouse/commit/7f893d47da7414045ec8fe96bcd98ab68081f2c5
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/sysregs.h
M inmates/lib/arm/timer.c
Log Message:
-----------
inmates, hypervisor: arm: prep timer library for AArch64
This patch is a minor touch up, that will allow to build the
ARM timer inmate library also on AArch64. We just need to add
the EL0 prefix to the CNTFRQ and CNTPCT sysregs, so we can
access them with the same code.
Commit: a996a83cd75d4ac19b3d7910fa43e2d109cd33ae
https://github.com/siemens/jailhouse/commit/a996a83cd75d4ac19b3d7910fa43e2d109cd33ae
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M inmates/Makefile
M inmates/demos/arm64/Makefile
M inmates/lib/arm64/Makefile
A inmates/lib/arm64/Makefile.lib
A inmates/lib/arm64/header.S
A inmates/lib/arm64/include/gic.h
A inmates/lib/arm64/include/inmate.h
A inmates/lib/arm64/include/mach-amd-seattle/mach/gic_v2.h
A inmates/lib/arm64/include/mach-amd-seattle/mach/timer.h
A inmates/lib/arm64/include/mach-amd-seattle/mach/uart.h
A inmates/lib/arm64/include/mach-foundation-v8/mach/gic_v2.h
A inmates/lib/arm64/include/mach-foundation-v8/mach/timer.h
A inmates/lib/arm64/include/mach-foundation-v8/mach/uart.h
A inmates/lib/arm64/inmate.lds
Log Message:
-----------
inmates: arm64: port imate demos from AArch32 to AArch64
This is a straight port of the inmate demos from AArch32 to AArch64.
These can now be loaded as cells onto a Foundation ARMv8 model.
Code reuse can possible be increased here as well.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: c28e1cb18e4010bd26ca90c99bf10fbabaac1007
https://github.com/siemens/jailhouse/commit/c28e1cb18e4010bd26ca90c99bf10fbabaac1007
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/irqchip.h
Log Message:
-----------
hypervisor: arm64: add work around for large SPIs on AMD Seattle
The AMD Seattle board features SPI ids that are larger than 64,
which we do not support properly. This workaround allows us to
demonstrate working cells on this target, until we have a proper fix.
This implies that only specific setups will be used on the
AMD Seattle; the IRQs for the uart and the second xgmac are being
passed to the cells.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: d979ea998afce4dbf769cdedaa684ac3d91f20d5
https://github.com/siemens/jailhouse/commit/d979ea998afce4dbf769cdedaa684ac3d91f20d5
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A configs/foundation-v8-uart-demo.c
Log Message:
-----------
hypervisor: arm64: add uart demo cell config for Foundation v8
Add a cell configuration file for the foundation-v8 model, to
be used with the PL011 UART inmate demo.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 4eabd8de9a6b8f5dada277bf4ed1f338bf1e76ea
https://github.com/siemens/jailhouse/commit/4eabd8de9a6b8f5dada277bf4ed1f338bf1e76ea
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A configs/foundation-v8-gic-demo.c
Log Message:
-----------
hypervisor: arm64: gic inmate cell config for foundation-v8
Add a cell configuration file for the gic inmate demo, for the
foundation-v8 model.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 9dd4225c6fbf041e0d42e1c49f15125528b849fe
https://github.com/siemens/jailhouse/commit/9dd4225c6fbf041e0d42e1c49f15125528b849fe
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A configs/amd-seattle-uart-demo.c
Log Message:
-----------
hypervisor: arm64: UART demo cell config for the AMD Seattle
Add a cell configuration file for the AMD Seattle development
board, to be used with the PL011 UART demo inmate.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 6a67e73b63a6bb4be7d31041f85f37c3af70c346
https://github.com/siemens/jailhouse/commit/6a67e73b63a6bb4be7d31041f85f37c3af70c346
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A configs/amd-seattle-gic-demo.c
Log Message:
-----------
hypervisor: arm64: gic demo cell config for the AMD Seattle
Add a cell configuration file to use on the AMD Seattle, to be
used with the gic demo inmate.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 104a53135912dae65f89bcaf4b7023ee399bd0ad
https://github.com/siemens/jailhouse/commit/104a53135912dae65f89bcaf4b7023ee399bd0ad
Author: Dmitry Voytik <dmitry...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M inmates/tools/arm64/Makefile
A inmates/tools/arm64/linux-loader.c
Log Message:
-----------
inmates: arm64: implement non-root linux loader
This patch implements a loader, that can be used to boot a Linux
kernel in a Jailhouse cell on AArch64.
Signed-off-by: Dmitry Voytik <dmitry...@huawei.com>
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
[antonios...@huawei.com:
- split foundation-v8 configuration to a separate patch
- small fixes in the linux loader output
- take kernel and dtb address using cell load command line ]
Commit: 1b516365e0b909dd55290e3f316c3421e5964fb5
https://github.com/siemens/jailhouse/commit/1b516365e0b909dd55290e3f316c3421e5964fb5
Author: Dmitry Voytik <dmitry...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A configs/foundation-v8-linux-demo.c
A samples/kernel-inmate-foundation-v8.dts
Log Message:
-----------
hypervisor: arm64: add linux inmate cell config for foundation-v8
Add the cell configuration files, and some helper scripts and device
tree for the foundation-v8 model. These can be used to load a linux
inmate on a cell on that target.
Signed-off-by: Dmitry Voytik <dmitry...@huawei.com>
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
[antonios...@huawei.com: split off as a separate patch,
some minor renaming for consistency]
Commit: 005430841176355e078d0e6715053b4690be7c54
https://github.com/siemens/jailhouse/commit/005430841176355e078d0e6715053b4690be7c54
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
A configs/amd-seattle-linux-demo.c
A samples/kernel-inmate-amd-seattle.dts
Log Message:
-----------
hypervisor: arm64: add linux inmate cell config for AMD Seattle
Add the cell configuration files, and some helper scripts and device
tree for the AMD Seattle development board. These can be used to
load a linux inmate on a cell on that target.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Commit: 3486e6fe28dffb6e7ec976ef6d8d00e07f4c37d2
https://github.com/siemens/jailhouse/commit/3486e6fe28dffb6e7ec976ef6d8d00e07f4c37d2
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M .travis.yml
M ci/build-all-configs.sh
M ci/gen-kernel-build.sh
A ci/kernel-config-amd-seattle
Log Message:
-----------
ci: Add support for arm64
This adds arm64 to CI via the AMD Seattle configuration.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: eaab4ce51fe1f68ae2f8666096a5a5fc48b7f087
https://github.com/siemens/jailhouse/commit/eaab4ce51fe1f68ae2f8666096a5a5fc48b7f087
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-01-25 (Mon, 25 Jan 2016)
Changed paths:
M driver/main.c
M hypervisor/hypervisor.lds.S
M hypervisor/include/jailhouse/header.h
M hypervisor/setup.c
Log Message:
-----------
core, driver: Pass rounded-up core size in hypervisor header
Hypervisor and root kernel may have different ideas about PAGE_SIZE.
This will cause wrong hypervisor core size calculations as seen on arm64
with 64K Linux PAGE_SIZE.
Avoid this trap by moving the round-up into the hypervisor code, passing
a ready-to-be-used size value in the header.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Compare: https://github.com/siemens/jailhouse/compare/06ab4106999c...eaab4ce51fe1
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