[siemens/jailhouse] de2978: inmates: x86: Make pm_timer_read SMP-safe
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Sep 16, 2015, 5:28:09 AM9/16/15
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Branch: refs/heads/next
Home: https://github.com/siemens/jailhouse
Commit: de2978af40886937a1b4181e5c4bff50d5f7520b
https://github.com/siemens/jailhouse/commit/de2978af40886937a1b4181e5c4bff50d5f7520b
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-16 (Wed, 16 Sep 2015)
Changed paths:
M inmates/lib/x86/timing.c
Log Message:
-----------
inmates: x86: Make pm_timer_read SMP-safe
Enable parallel usage of pm_timer_read on different cell CPUs by making
the last value and the overflow sum per-cpu variables.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 8aec53690eb9034d8971dd86c887c7e8be6adc45
https://github.com/siemens/jailhouse/commit/8aec53690eb9034d8971dd86c887c7e8be6adc45
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-16 (Wed, 16 Sep 2015)
Changed paths:
M inmates/lib/x86/inmate.h
M inmates/lib/x86/timing.c
Log Message:
-----------
inmates: x86: Add support for TSC-based timing
Provide a service to calibrate the TSC against the PM timer and read out
the current time in nanoseconds. This service is much faster than the
slow PM timer, and it's also not affected by chipset-induced delays.
Note that the simplistic algorithm only supports measuring relative time
spans of a couple of seconds.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: af7dc41056d48d82a470269f9298edff2dc4970f
https://github.com/siemens/jailhouse/commit/af7dc41056d48d82a470269f9298edff2dc4970f
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-16 (Wed, 16 Sep 2015)
Changed paths:
M inmates/demos/x86/apic-demo.c
Log Message:
-----------
inmates: x86: Switch apic-demo to TSC time measurement
Removes chipset-related latency sources from the APIC timer interrupt
benchmark, enabling extremely low jitters (e.g. < 1µs on a Xeon D-1540).
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 9dba4aed76c0e70b6fda13f15e2ee0a3c76f8461
https://github.com/siemens/jailhouse/commit/9dba4aed76c0e70b6fda13f15e2ee0a3c76f8461
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-16 (Wed, 16 Sep 2015)
Changed paths:
M hypervisor/arch/x86/vmx.c
Log Message:
-----------
x86: vmx: Micro-cleanup in vcpu_vendor_cell_init
Return the error code directly instead of take the indirect route via
pre-initialized err variable. Avoids that some refactoring once destroys
this relationship.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: b0e784bf9793152cdd952736af78e779a4f94dc2
https://github.com/siemens/jailhouse/commit/b0e784bf9793152cdd952736af78e779a4f94dc2
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-16 (Wed, 16 Sep 2015)
Changed paths:
M hypervisor/arch/x86/include/asm/processor.h
M hypervisor/arch/x86/paging.c
M hypervisor/arch/x86/setup.c
M hypervisor/arch/x86/svm.c
M hypervisor/arch/x86/vcpu.c
M hypervisor/arch/x86/vmx.c
Log Message:
-----------
x86: Add sub-leaf selection parameter to cpuid_*
This allows to call cpuid also on specific sub-leaves. Will be used
first for CAT.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 278c3f585db18eba153c5baa19cbcbc2fa4a8f84
https://github.com/siemens/jailhouse/commit/278c3f585db18eba153c5baa19cbcbc2fa4a8f84
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-16 (Wed, 16 Sep 2015)
Changed paths:
M hypervisor/arch/x86/vmx.c
Log Message:
-----------
x86: vmx: Block write access to CAT MSRs
Make sure the cells cannot mess around with them, modifying the
configuration the hypervisor chose.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: c5e71f2ae0c0a00deaf51a17accbd30b9eeb36c6
https://github.com/siemens/jailhouse/commit/c5e71f2ae0c0a00deaf51a17accbd30b9eeb36c6
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-16 (Wed, 16 Sep 2015)
Changed paths:
M hypervisor/include/jailhouse/cell-config.h
M tools/jailhouse-cell-linux
Log Message:
-----------
core, tools: Introduce cache regions to the cell configuration
Allow to specify regions of caches so that the hypervisor can partition
their usage accordingly whenever the hardware supports this.
The specification of their start location and sizes depend on the
architecture specific partitioning support. So far, L1-L3 cache types
are definable (of which Intel's CAT will only support L3). As with
memory regions, caches are usually taken from the root cell on non-root
cell creation, but they can also be declared as shared with the root
cell.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 7af65b1cf1867c4a083056c907e16555bc6f7ad9
https://github.com/siemens/jailhouse/commit/7af65b1cf1867c4a083056c907e16555bc6f7ad9
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-16 (Wed, 16 Sep 2015)
Changed paths:
M hypervisor/arch/x86/Makefile
A hypervisor/arch/x86/cat-stubs.c
A hypervisor/arch/x86/cat.c
M hypervisor/arch/x86/control.c
A hypervisor/arch/x86/include/asm/cat.h
M hypervisor/arch/x86/include/asm/cell.h
M hypervisor/arch/x86/include/asm/percpu.h
M hypervisor/arch/x86/include/asm/processor.h
M hypervisor/arch/x86/setup.c
Log Message:
-----------
x86: Introduce Cache Allocation Technology support for Intel CPUs
CAT is a CPU feature first added to Xeon D and certain Xeon E5 v3
processors. It so far allows to specify access restrictions to the L3
cache, including complete isolation between different entities.
This adds CAT control to Jailhouse on a per-cell level. The user is free
to specify a contiguous access mask for each cell, use that mask
exclusively (typical case), share any overlaps with the root cell
(JAILHOUSE_CACHE_ROOTSHARED), or simply use the root cell mask. If
nothing else is specified, the root cell uses the full cache (until
non-root cells shrink it).
Due to the hardware-induced requirement to have a contiguous bitmask,
shrinking the root mask on cell creation and extending it again on
destruction is not trivial.
When creating a new cell, we may punch a whole into the root mask. In
that case, we also subtract the smaller remaining half from it.
When restoring the root mask on cell destruction, we choose a simple
algorithm that first collects all released bits in a combined mask, then
tries to merge that mask bit-wise with the current root cell mask. On
success we restart the freed mask walk to ensure that all contiguous
bits are merged.
A lot of complication, despite we already require explicit mask
allocation. Let's just hope that there is a noteworthy benefit in
restricting CAT bitmasks in hardware this way.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 5efc2c56086339716b6b0424eccd248f937f8fe0
https://github.com/siemens/jailhouse/commit/5efc2c56086339716b6b0424eccd248f937f8fe0
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-16 (Wed, 16 Sep 2015)
Changed paths:
M configs/apic-demo.c
M configs/linux-x86-demo.c
M configs/tiny-demo.c
Log Message:
-----------
configs: Add cache region to x86 demo cells
Assuming we have more than 4 units of L3 cache on systems that support
L3 partitioning, assign the first unit (e.g. 1 MB on a Xeon D 1540) to
apic-demo, the second to tiny-demo and the succeeding 2 to the non-root
Linux config. The latter is supposed to improve the Linux cell latencies
while the former two are not (they are expected to stay in L1/L2 due to
their sizes) but serve as test cases for the partitioning management
logic.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 47f24159ba4216e77e2b644ee2df447b5b007b70
https://github.com/siemens/jailhouse/commit/47f24159ba4216e77e2b644ee2df447b5b007b70
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-16 (Wed, 16 Sep 2015)
Changed paths:
M TODO.md
Log Message:
-----------
TODO: Remove CAT item
Feature is now available.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Compare: https://github.com/siemens/jailhouse/compare/4783279c2167...47f24159ba42
Home: https://github.com/siemens/jailhouse
Commit: de2978af40886937a1b4181e5c4bff50d5f7520b
https://github.com/siemens/jailhouse/commit/de2978af40886937a1b4181e5c4bff50d5f7520b
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-16 (Wed, 16 Sep 2015)
Changed paths:
M inmates/lib/x86/timing.c
Log Message:
-----------
inmates: x86: Make pm_timer_read SMP-safe
Enable parallel usage of pm_timer_read on different cell CPUs by making
the last value and the overflow sum per-cpu variables.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 8aec53690eb9034d8971dd86c887c7e8be6adc45
https://github.com/siemens/jailhouse/commit/8aec53690eb9034d8971dd86c887c7e8be6adc45
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-16 (Wed, 16 Sep 2015)
Changed paths:
M inmates/lib/x86/inmate.h
M inmates/lib/x86/timing.c
Log Message:
-----------
inmates: x86: Add support for TSC-based timing
Provide a service to calibrate the TSC against the PM timer and read out
the current time in nanoseconds. This service is much faster than the
slow PM timer, and it's also not affected by chipset-induced delays.
Note that the simplistic algorithm only supports measuring relative time
spans of a couple of seconds.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: af7dc41056d48d82a470269f9298edff2dc4970f
https://github.com/siemens/jailhouse/commit/af7dc41056d48d82a470269f9298edff2dc4970f
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-16 (Wed, 16 Sep 2015)
Changed paths:
M inmates/demos/x86/apic-demo.c
Log Message:
-----------
inmates: x86: Switch apic-demo to TSC time measurement
Removes chipset-related latency sources from the APIC timer interrupt
benchmark, enabling extremely low jitters (e.g. < 1µs on a Xeon D-1540).
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 9dba4aed76c0e70b6fda13f15e2ee0a3c76f8461
https://github.com/siemens/jailhouse/commit/9dba4aed76c0e70b6fda13f15e2ee0a3c76f8461
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-16 (Wed, 16 Sep 2015)
Changed paths:
M hypervisor/arch/x86/vmx.c
Log Message:
-----------
x86: vmx: Micro-cleanup in vcpu_vendor_cell_init
Return the error code directly instead of take the indirect route via
pre-initialized err variable. Avoids that some refactoring once destroys
this relationship.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: b0e784bf9793152cdd952736af78e779a4f94dc2
https://github.com/siemens/jailhouse/commit/b0e784bf9793152cdd952736af78e779a4f94dc2
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-16 (Wed, 16 Sep 2015)
Changed paths:
M hypervisor/arch/x86/include/asm/processor.h
M hypervisor/arch/x86/paging.c
M hypervisor/arch/x86/setup.c
M hypervisor/arch/x86/svm.c
M hypervisor/arch/x86/vcpu.c
M hypervisor/arch/x86/vmx.c
Log Message:
-----------
x86: Add sub-leaf selection parameter to cpuid_*
This allows to call cpuid also on specific sub-leaves. Will be used
first for CAT.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 278c3f585db18eba153c5baa19cbcbc2fa4a8f84
https://github.com/siemens/jailhouse/commit/278c3f585db18eba153c5baa19cbcbc2fa4a8f84
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-16 (Wed, 16 Sep 2015)
Changed paths:
M hypervisor/arch/x86/vmx.c
Log Message:
-----------
x86: vmx: Block write access to CAT MSRs
Make sure the cells cannot mess around with them, modifying the
configuration the hypervisor chose.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: c5e71f2ae0c0a00deaf51a17accbd30b9eeb36c6
https://github.com/siemens/jailhouse/commit/c5e71f2ae0c0a00deaf51a17accbd30b9eeb36c6
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-16 (Wed, 16 Sep 2015)
Changed paths:
M hypervisor/include/jailhouse/cell-config.h
M tools/jailhouse-cell-linux
Log Message:
-----------
core, tools: Introduce cache regions to the cell configuration
Allow to specify regions of caches so that the hypervisor can partition
their usage accordingly whenever the hardware supports this.
The specification of their start location and sizes depend on the
architecture specific partitioning support. So far, L1-L3 cache types
are definable (of which Intel's CAT will only support L3). As with
memory regions, caches are usually taken from the root cell on non-root
cell creation, but they can also be declared as shared with the root
cell.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 7af65b1cf1867c4a083056c907e16555bc6f7ad9
https://github.com/siemens/jailhouse/commit/7af65b1cf1867c4a083056c907e16555bc6f7ad9
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-16 (Wed, 16 Sep 2015)
Changed paths:
M hypervisor/arch/x86/Makefile
A hypervisor/arch/x86/cat-stubs.c
A hypervisor/arch/x86/cat.c
M hypervisor/arch/x86/control.c
A hypervisor/arch/x86/include/asm/cat.h
M hypervisor/arch/x86/include/asm/cell.h
M hypervisor/arch/x86/include/asm/percpu.h
M hypervisor/arch/x86/include/asm/processor.h
M hypervisor/arch/x86/setup.c
Log Message:
-----------
x86: Introduce Cache Allocation Technology support for Intel CPUs
CAT is a CPU feature first added to Xeon D and certain Xeon E5 v3
processors. It so far allows to specify access restrictions to the L3
cache, including complete isolation between different entities.
This adds CAT control to Jailhouse on a per-cell level. The user is free
to specify a contiguous access mask for each cell, use that mask
exclusively (typical case), share any overlaps with the root cell
(JAILHOUSE_CACHE_ROOTSHARED), or simply use the root cell mask. If
nothing else is specified, the root cell uses the full cache (until
non-root cells shrink it).
Due to the hardware-induced requirement to have a contiguous bitmask,
shrinking the root mask on cell creation and extending it again on
destruction is not trivial.
When creating a new cell, we may punch a whole into the root mask. In
that case, we also subtract the smaller remaining half from it.
When restoring the root mask on cell destruction, we choose a simple
algorithm that first collects all released bits in a combined mask, then
tries to merge that mask bit-wise with the current root cell mask. On
success we restart the freed mask walk to ensure that all contiguous
bits are merged.
A lot of complication, despite we already require explicit mask
allocation. Let's just hope that there is a noteworthy benefit in
restricting CAT bitmasks in hardware this way.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 5efc2c56086339716b6b0424eccd248f937f8fe0
https://github.com/siemens/jailhouse/commit/5efc2c56086339716b6b0424eccd248f937f8fe0
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-16 (Wed, 16 Sep 2015)
Changed paths:
M configs/apic-demo.c
M configs/linux-x86-demo.c
M configs/tiny-demo.c
Log Message:
-----------
configs: Add cache region to x86 demo cells
Assuming we have more than 4 units of L3 cache on systems that support
L3 partitioning, assign the first unit (e.g. 1 MB on a Xeon D 1540) to
apic-demo, the second to tiny-demo and the succeeding 2 to the non-root
Linux config. The latter is supposed to improve the Linux cell latencies
while the former two are not (they are expected to stay in L1/L2 due to
their sizes) but serve as test cases for the partitioning management
logic.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 47f24159ba4216e77e2b644ee2df447b5b007b70
https://github.com/siemens/jailhouse/commit/47f24159ba4216e77e2b644ee2df447b5b007b70
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-16 (Wed, 16 Sep 2015)
Changed paths:
M TODO.md
Log Message:
-----------
TODO: Remove CAT item
Feature is now available.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Compare: https://github.com/siemens/jailhouse/compare/4783279c2167...47f24159ba42
GitHub
Sep 25, 2015, 2:20:56 PM9/25/15
to jailho...@googlegroups.com
Branch: refs/heads/master
Commit: 70e2f4b2fe87fa5ff895b2ae8ef2e8ae78cbb0c7
https://github.com/siemens/jailhouse/commit/70e2f4b2fe87fa5ff895b2ae8ef2e8ae78cbb0c7
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-18 (Fri, 18 Sep 2015)
Changed paths:
M hypervisor/pci.c
Log Message:
-----------
core: pci: Fix MMCONFIG handling for root cell
Reorder the initialization in pci_init so that MMCONFIG is set up before
pci_cell_init is invoked for the root cell. Calling pci_cell_init
earlier has the undesired effect that the MMCONFIG region is not
registered for the root cell, and all related accesses will fail with
generic MMIO errors.
This is a regression of e17d52525d.
Reported-by: Yijun Zhu <zhuy...@huawei.com>
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 61a1b18531f374723ab7303e4feb53744f0c6eaa
https://github.com/siemens/jailhouse/commit/61a1b18531f374723ab7303e4feb53744f0c6eaa
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-18 (Fri, 18 Sep 2015)
Changed paths:
M hypervisor/pci.c
Log Message:
-----------
core: pci: Fix format string of MMCONFIG error reporting
The config space address was not printed.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Compare: https://github.com/siemens/jailhouse/compare/1e1d35a17f4e...61a1b18531f3
https://github.com/siemens/jailhouse/commit/70e2f4b2fe87fa5ff895b2ae8ef2e8ae78cbb0c7
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-18 (Fri, 18 Sep 2015)
Changed paths:
M hypervisor/pci.c
Log Message:
-----------
core: pci: Fix MMCONFIG handling for root cell
Reorder the initialization in pci_init so that MMCONFIG is set up before
pci_cell_init is invoked for the root cell. Calling pci_cell_init
earlier has the undesired effect that the MMCONFIG region is not
registered for the root cell, and all related accesses will fail with
generic MMIO errors.
This is a regression of e17d52525d.
Reported-by: Yijun Zhu <zhuy...@huawei.com>
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 61a1b18531f374723ab7303e4feb53744f0c6eaa
https://github.com/siemens/jailhouse/commit/61a1b18531f374723ab7303e4feb53744f0c6eaa
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2015-09-18 (Fri, 18 Sep 2015)
Changed paths:
M hypervisor/pci.c
Log Message:
-----------
core: pci: Fix format string of MMCONFIG error reporting
The config space address was not printed.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Compare: https://github.com/siemens/jailhouse/compare/1e1d35a17f4e...61a1b18531f3
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