FPGA 1130
John McKee
Lots of questions. But, just a simple (?) one for starters - How did the FPGA 1130 get created? That is not so simple, I guess. But, I am wondering about the process of generating the logic. What do the tables look like?
John McKee
Dave G4UGM
>But, just a simple (?) one for starters - How did the FPGA 1130 get created?
Some wrote it perhaps? Actually the code say “© Richard T Stofer” but I guess you knew that.
Note it is written in VHDL whereas I think the article you read has Verilog examples.
They are similar but different.
Just to put that question in perspective its almost like asking “how does the “C” compiler work”
>That is not so simple, I guess. But, I am wondering about the process of generating the logic.
Well the logic is generated by the “logic synthesiser” from the logic description language. When the 1130 code is built for Spartan 3, then that’s usually a program called XST.
> What do the tables look like?
The actual generated tables that get loaded into the FPGA, I don’t think you can see them…
.. the VHDL that generates them looks a bit like “C” or Algol and implements a state machine.
So looking at the Baby or SSEM a simpler computer that understands only seven instructions..
https://en.wikipedia.org/wiki/Manchester_Small-Scale_Experimental_Machine
The logic manuals are all here:-
http://www.cs.man.ac.uk/CCS/SSEM/volunteers/index.html
And here is a snippet from the FPGA code I wrote to emulate the machine. The IBM 1130 code is much longer and I guess was written from the CPU logic manuals…
“F_STATS” is the function code from the current instruction,
CI is the “Current Instruction” or program counter,
ACC is the accumulator,
“DOUTB” is the content of the memory addressed by the current instruction
“DINB” is the word that will be written
if( ( (run = '1') and (halted = '0') ) or (Single_step = '1') )then
case F_STATS is
when "000" => --- JMP
CI <= doutb ( 4 downto 0);
when "001" => --- Indirect relative JMP
CI <= CI + doutb ( 4 downto 0);
when "010" => --- Load Negative
ACC <= "00000000000000000000000000000000" - doutb ;
when "011" => --- Store
-- DINB <= ACC; -- write this elsewhere
wr_store <= "1"; -- set flag to show ACC needs to be stored
when "100" => --- Subtract
ACC <= ACC - doutb;
when "101" => --- Also subtract
ACC <= ACC - doutb;
when "110" => --- Test accumulator -ve
TEST <= ACC(31);
when "111" => --- Halt
halted <= '1';
-- led0 <= '1'; (This is actually set elsewhere)
null;
when others =>
null;
end case;
end if;
And you can see the FPGA code running here:-
https://www.youtube.com/watch?v=ALXax3Gydl8
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John McKee
John McKee
Dave G4UGM
I am glad you found it helpful. I will just add that there are actually two ways to implement an historic computer in FPGA logic. Richard’s implementation is basically “functionally equivalent” so it runs IBM1130 code but the generated logic may not look like a real IBM1130. Carl Claunch
http://ibm1130.blogspot.co.uk/
was working on a gate level implementation, so implementing each gate on a real IBM1130 in an FPGA. Much harder to achieve but he has paused as he now owns a real IBM1130…
.. Laurence Wilkinson has done a similar job for the 360/30 here:-
http://www.ljw.me.uk/ibm360/vhdl/
there are many others around for most popular systems including PDP-8 and PDP-11 and of course the various 8 and 16 bit micros such as the 6800 and 8080…
Dave
Richard Stofer
Well, I wrote it. Yup! That’s me in the video. I’m going to be a STAR!
Ok, enough of that…
Way back in the early ‘70s, I decided I wanted an 1130. I had left the company where I had unlimited access to a real 1130 so I grabbed what information I could find and tried to create the CPU using TTL logic and blown-link proms for microcode. Unfortunately, the 2102 static ram chip had yet to come to the hobby level. So, I bought the Altair 8800…
After I retired in 2003, I took another look at the project and decided that FPGAs were approachable. Synthesis software was free and the price for boards was high but doable. It is worth noting that I knew absolutely nothing about FPGAs and not very much about the internals of the 1130. I still don’t know very much about FPGA programming – just barely enough to create some finite state machines and static logic. I wasn’t working entirely blind, I did go to EE school and I knew a little about logic design.
I used ONLY the “Functional Characteristics” manual, I didn’t have the logic diagrams. If I had those diagrams, the project never would have worked. FPGAs want to operate in a synchronous manner (clocked) and the real 1130 uses a lot of asynchronous (non-clocked) logic typical of the era. For those who follow this kind of thing, the SLT logic blocks used RS flops instead of D or JK flops. Not all flops were clocked and the clock was gated, something FPGAs don’t like very much. Carl Claunch experimented with FPGAs and asynchronous logic and I’m not sure how it all turned out. I did note that he just went out and bought the real machine! Lucky fellow…
I wrote the code for each instruction, one by one. Operand fetch is the most difficult due to indexing, indirection and short/long addressing but once that is worked out, logic for the individual instructions is pretty straight forward. Except for signed non-restoring division. That took a LOT of research and I finally found THE book – one that had a kind of microcode for the process. Works well.
Now the ugly part: My core is not anywhere near what an actual 1130 looks like. I don’t take the same number of cycles per instruction and mine runs at 50 MHz versus 400 kHz. I think Carl’s project was cycle-for-cycle faithful to the original design.
Yes, there’s a lot of code. It is over 10k lines including the peripherals. A good programmer could probably cut it in half. Mine is written in what I consider to be a Behavioral mode. There is nothing written at the gate level and no consideration is given to the architecture of the LUTs (LookUp Table) in each cell. I have seen designs where that is done and the code is elegant. It is also nearly impossible to figure out how anything actually works. I suppose one of my old professors would describe my code as something written by a FORTRAN programmer in a PL/I world! Note: that actually happened in grad school when I wrote an 8080 assembler as an independent study project. I have so much to learn…
As I said in the video, this project would have been a good deal more difficult were it not for Brian’s simulator and, more specifically, his assembler. It’s not like the logic worked without testing!
I saw that Nuts & Volts article in an email promotion yesterday. I’ll get the magazine in a week or so. The code is for a 4 line decoder. It is static, nothing is clocked and there certainly isn’t any state machines. Nor should there be for a decoder.
Like any programming project, there are ‘patterns’. We don’t even thing when we write DO { … } WHILE <> loops. FOR loops just flow right out of the keyboard. It’s pretty much the same with VHDL (which I use) and Verilog. You learn a few constructs, you design a simple project and then you extend it. Just like FORTRAN programs of yesteryear. We started by computing the area of a circle, then we moved on to bigger and better things.
I had a simple goal for the project: I wanted to play 3D Tic-Tac-Toe on the console device. Seriously! That was the end goal. But to do that, I wanted to be faithful to the 1130 design in so far as running all of the IBM code unchanged. That was key! There was already an OS and a FORTRAN compiler. I wanted all of that to work as written.
And, yes, the code is always available. Drop me an email so I know where to send it. But before jumping in, there is an attachment board to the Digilent Nexys 2 board. This attachment has a 4 port Serial->USB gadget and a 50 pin socket for the Compact Flash. I have the ExpressPCB design but I don’t have any spare boards or sockets. And the Nexys 2 board is now out of production. So is the Nexys 3. The Nexys 4 board is workable but it is too expensive. Some market research is necessary. Maybe something from http://www.ztex.de The code itself is mostly portable but there are issues concerning CPU memory – I have no idea how to deal with DDR memory (and most DDR controller cores are licensed for $$$) and that seems to be what all the newer boards are using. I used boards with static ram or CellularRam (can be operated as static ram). Bottom line: I don’t know how to replicate the project with the FPGA boards I know about. It’s possible but it might be tedious.
A side note: Debugging VHDL is a great deal more difficult than debugging FORTRAN! I don’t have a simulator and, even if I did, it’s not MY hardware. A logic analyzer is a requirement. A smarter person than I would build the LA inside the project. My boards at the time had 3-32 bit bus connectors so I had one spare to connect to a LA. These days those wide ports don’t seem to be as available.
Richard
Carl Claunch
I agree with everything Richard said. Debugging is hard work.
Richard Stofer
One solution to the DDR problem on modern boards is to select a board with an FPGA that has enough internal BlockRam so that external RAM is not required. This isn’t all that hard these days. At the moment there is a rather large priority tree acting as an arbiter for DMA memory access from the CPU and peripherals. This may slow down the CPU every now and then (cycle stealing, more or less). Using internal BlockRam is much better because it is dual-port. The CPU is on one side and the DMA channel is on the other. No contention exists because there is no reason for the CPU to access the memory used by the various IO buffers until the IO operation is complete. Very cool!
At the moment, the only device using BlockRam is a fifo for the card reader. I would have to think about how much BlockRam was needed and whether the fifo could be moved to distributed ram.
My current project is to add 2 ea 2311 drives to the system. This adds another 10 volumes to the one in the CPU. Lots of storage! And the complication of 3 logical devices trying to access just one physical CF device. I may change my mind on this and use two SD devices for the 2311s even though they will be a good deal slower. The logic is a lot simpler.
Richard
John McKee
--
Carl Claunch
Richard Stofer
At one level, a hardware description language like VHDL is quite similar to any other computer language. The one really HUGE difference is that everything, and I mean EVERYTHING, is happening in parallel. It is only by introducing finite state machines that we can create a sequential operation. It takes time to wrap your head around the fact that even though the code is written top to bottom, it is all running in parallel. Kind of like a gazillion core processor.
Like the logic constructs of any computer language, there are certain logical constructs, starting at the gate level, working through function blocks like decoders, muxes and registers all the way up to FSAs. Since a computer is a sequential machine, you can bet there are dozens and dozens of FSAs. One FSA kicks off another FSA that runs until complete – that kind of thing. In my case, the 1130 CPU is encoded as one gigantic FSA with a little over 100 states. Several states fetch the instruction and operand (if any), a few more states perform the operation and the FSA branches back to ‘fetch’.
I took a very brief look at the 1401 and I don’t have a clue about how to create one. I would have to sit down and figure out every instructions with all of the options. It would take awhile to wrap my head around what is going on. But, it is definitely doable. The 1401 is a digital system and there’s no reason it couldn’t be recreated in an FPGA. It’s just logic. I would try to diagram (at least mentally) how my state machine would execute each instruction and how there might be side states depending on certain encodings. In the end, I would have a gigantic FSA – just like the 1130 but different. Somebody did it! IBM built the machine…
It might be interesting to follow along with the FPGA series in Nuts and Volts. The board itself is available from SparkFun for $75 which is pretty cheap for the education. It is not a large enough FPGA to replicate the 1130. But there is a lot of learning that goes into just about anything and this is a place to start.
https://www.sparkfun.com/products/11953
The board requires the Xilinx toolchain called WebPack ISE. The Sparkfun tutorial shows how to download and license the software. Be aware that the latest version of ISE is the last version there will ever be. Xilinx has moved to Vivado and it’s not free. The Altera software was free and there are Altera boards around. Didn’t Intel just buy Altera?
First you create some static logic like Output <= InA AND InB; and watch that work.
Then you create a decoder like the N&V article
Next you might create a mux – maybe start with 4 inputs 1 bit wide and expand it to many inputs by very wide. The A-Bus MUX in my 1130 has 26 inputs of 16 bits each.
… this about complete the static logic … There just aren’t a lot of other constructs.
Now you can play around with D-flops. They will require a clocked process
Next you create a register. This is nothing but a really wide D-flop.
Now that you have a register to retain the present state info, you can build an FSA. Set up some input pins, some output pins and watch it run.
Once you have a working FSA, you are off to the races. All you need are bigger FSAs! Lots of ‘em.
There are some great online resources (tutorials) re: Verilog and VHDL. I started with VHDL and I just don’t ‘get’ Verilog. OTOH, I have never really tried to use it. It must work because at least half of the logic in the world is being written in Verilog.
“Essential VHDL” by Sundar Rajan may be helpful.
Richard
From: ibm...@googlegroups.com [mailto:ibm...@googlegroups.com] On Behalf Of John McKee
Sent: Thursday, June 18, 2015 8:33 AM
To: ibm...@googlegroups.com
Subject: Re: [IBM1130] FPGA 1130
Maybe my level of "fascination" is way low, but FPGA and what has been presented reminds me of how I felt when I first saw the 1130 used to play a game - Battle of the Numbers when I got out of high school and needed a nudge toward a career of some sort. Some things look really complicated when the observer has no knowledge of the peocess. I think it was the article that I mentioned that described FPGA as hardware programming. Just another application, in a way.
John McKee
Richard Stofer
I see I overlooked your question about ‘tables’. What tables? In the very old days of microcode, the entire processors was driven from a set of PROMS and, indeed, this was a gigantic table with all kinds of control bits and next state addressing. Today, I think you can write VHDL as microcode but I don’t think anybody does it. It’s just too hard to keep track of all the details. Then somebody comes along and wants to reduce the size/cost of the PROM!
We know that the interrupt system in the 1130 has a priority scheme. There is a logical construct called a priority tree which in any other language looks like
If <this> then
That
Elseif <some other condition> then
Something else
Else
Whatever
It turns out that the 1130 interrupt priority scheme looks EXACTLY like that:
-- generate main ILSW from individual ILSW's based on priority
process(IntServLevel, ILSW0, ILSW1, ILSW2, ILSW3, ILSW4, ILSW5)
begin
if IntServLevel(0) = '1' then
ILSW <= ILSW0;
elsif IntServLevel(1) = '1' then
ILSW <= ILSW1;
elsif IntServLevel(2) = '1' then
ILSW <= ILSW2;
elsif IntServLevel(3) = '1' then
ILSW <= ILSW3;
elsif IntServLevel(4) = '1' then
ILSW <= ILSW4;
elsif IntServLevel(5) = '1' then
ILSW <= ILSW5;
else
ILSW <= x"0000";
end if;
end process;
So, if there is an interrupt on IntServLevel(0) then the ILSW that the CPU will test comes from ILSW0 else in IntServLevel(1) …
Note how the elsif enforces the priority tree and how the default sets the ILSW to 0.
-- manage ISL vector
process(Reset, Clk, ISL_Ctrl)
begin
if Reset = '1' then
IntServLevel <= (others => '0');
elsif rising_edge(Clk) then
case ISL_Ctrl is
when ISL_NOP => null;
when ISL_CLEAR_HIGHEST => if IntServLevel(0) = '1' then
IntServLevel(0) <= '0';
elsif IntServLevel(1) = '1' then
IntServLevel(1) <= '0';
elsif IntServLevel(2) = '1' then
IntServLevel(2) <= '0';
elsif IntServLevel(3) = '1' then
IntServLevel(3) <= '0';
elsif IntServLevel(4) = '1' then
IntServLevel(4) <= '0';
elsif IntServLevel(5) = '1' then
IntServLevel(5) <= '0';
end if;
when ISL_SET_LEVEL => if IntReqLevel(0) = '1' then
IntServLevel(0) <= '1';
end if;
if IntReqLevel(1) = '1' then
IntServLevel(1) <= '1';
end if;
if IntReqLevel(2) = '1' then
IntServLevel(2) <= '1';
end if;
if IntReqLevel(3) = '1' then
IntServLevel(3) <= '1';
end if;
if IntReqLevel(4) = '1' then
IntServLevel(4) <= '1';
end if;
if IntReqLevel(5) = '1' then
IntServLevel(5) <= '1';
end if;
when others => null;
end case;
end if;
end process;
Somewhere in the big state machine, an ISL_Ctrl command is generated (it’s really just a 2 bit wide logic vector). Normally it is set to ISL_NOP and this logic does nothing. Every once in awhile we want to set the IntServLevel so a command of ISL_SET_LEVEL is generated for exactly one clock cycle. The various IntReqLevels are loaded broadside into the IntServLevel register (just a 5 bit wide register) and processed in the priority tree above. When it comes time to clear an IntServLevel, an INT_CLEAR_LEVEL command is generated and ONLY the highest priority IntServLevel is reset. That’s correct because the CPU was always processing the highest level.
There’s a lot of this kind of stuff in the CPU. The point to all of this is that VHDL and Verilog look a whole lot like any other language. There’s nothing in the code that even resembles wire-wrapping. If I need another 16 bit vector (which could become a register in a clocked process) it is defined like this:
signal ACC : std_logic_vector(15 downto 0); -- accumulator
That’s it! No trip to the store for more chips, just add a line of code and we have an accumulator register.
Richard
On Thu, Jun 18, 2015 at 12:00 AM, John McKee <jmmc...@gmail.com> wrote:
I skimmed an article in the latest issue of "Nuts and Volts" about FPGA. It did not get into a lot of detail. I saw the recorded presentation of the FPGA implementation of the 1130 that was presented at 1130.org.
Lots of questions. But, just a simple (?) one for starters - How did the FPGA 1130 get created? That is not so simple, I guess. But, I am wondering about the process of generating the logic. What do the tables look like?
John McKee
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Richard Stofer
Regarding the Nuts and Volts FPGA article in the July 2015 edition, here is the decoder logic written in VHDL without the Enable input:
use IEEE.STD_LOGIC_1164.ALL;
Port ( input : in STD_LOGIC_VECTOR (1 downto 0);
output : out STD_LOGIC_VECTOR (3 downto 0));
end Decoder;
"0010" when input = "10" else
"0100" when input = "01" else
"1000";
end Behavioral;
NET "output<3>" LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;
NET "input<1>" LOC = "M13" | IOSTANDARD = LVCMOS33 | PULLUP ;