I have never used CPRT CEND and I wonder what is happening to Working Storage – maybe nothing…
I would put the //XEQ right after the ‘end’ statement and skip the CPRT stuff just to test.
OR, I would save the WS to UA and execute it later as a named program.
I didn’t implement the punch on my FPGA version so I have no independent hardware for testing.
I guess I could try compiling to WS, use the CPRT/CEND cards and try to execute from WS. Maybe later, I have a barbecue to get started. I expect to overindulge in Miller Genuine Draft so maybe tomorrow.
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// CPRINT
Makes the console printer the principal output device
// CEND
Ends console printer output and restores the primary printer as principal output device.
Ahh, thanks. With Cytos that would be “sysout here” and “sysout p1403/p1132”.
That stands for Conversational Yale Terminal Operating System. It was written by Tim Mellon and is available with my 1130 emulator running TSO (Time Sharing Option for the IBM 1130) which I sent out a few years ago.
Hmm, I had it in Dropbox but I see it is not there anymore. I’ll put it back.
Eddy
My 1130 emulator plus CYTOS, TSO, EMU Fortran and more are here. https://www.dropbox.com/preview/1830%20release/Distrobution/Distrobution.rar?role=personal
I’m not aware of such a thing but it should be possible to try to get the current datasheets and more closely approach the timing limits. It should also be possible to put a FIFO between the CPU and disk or mess around with the DMA channel to take out some cycles or give the disk the ability to transfer more than one word at a time.
Perhaps a higher clock speed would result in coming close to the CF timing limits. Or at least some submultiple might be closer.
I basically got the component to work, chose CF cards that worked (and not all do) and left it at that. I’m running about 125 times faster than the real machine so I figured I had gone far enough. Doubling the clock to 100 MHz on the newer Artix A7s should be possible. I left in the IO delays such that all input/output runs in 1130 time. Brian warned me not to push it because there are certain assumptions made in the code about how long it will be before a completion interrupt occurs and the code expects to complete a certain number of instructions before that occurs. I didn’t push it.
Speaking of intentional delays, it turns out that I have a 1ms access timer slowing the CF.
process(Clk, LoadAccessTimer)
begin
if rising_edge(Clk) then
if LoadAccessTimer = '1' then -- x"1F590" - 5 mS
-- AccessTimer <= x"061A8"; -- about 1 mS, assume 0 rotational delay
AccessTimer <= x"00010";
else
if AccessTimer /= 0 then
AccessTimer <= AccessTimer - 1;
end if;
end if;
end if;
end process;
I wonder what would happen if I eliminated this…
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