dBFS level with rtl-sdr

[Luigi Tarenga]

Hello,
I'm writing a small guide (in italian) for my ham club about sdr in general.
I'm also inclusing some formula about how to calculate le noise floor on a given device
known some of it's internals, specification and configuration in the software used.
I would like to use the rtl-sdr dongle as example because is the most affordable for new
users.
So, as a general rule of thumb the noise floor seen on the panadater with minimum amplification
and a 50 Ohm dummy load as antenna (or disconnected) should be given by the quantization noise:
NF = -6.02*8-1.76-10log(FFT bin size / 2)
but I think this formula is missing something in the case of the rtl-sdr since in the case
of r820t tuner a single IF on the I branch is sampled at 28.8 MSPS and then this is digital down
converted and decimated. So I tried to figure out the gain process as:
10log(28.8/2/3.2) ~= 6.5 dB as process gain. This seems to fit with what I see on the panadapter
of gqrx. I get about -92 dBFS with 2.4 MSPS, 0 LNA, and FFT of 8192.

Now the question for this group: there is a correction value, default offset or formula used in
gqrx code that take account of hardware implementation when displaying value on the dBFS scale?
and what are your opinion on my calculation?

thank you very much in advance
Luigi

[Kevin Reid]

On Wed, Nov 23, 2016 at 5:42 AM, Luigi Tarenga <luigi....@gmail.com> wrote:

So, as a general rule of thumb the noise floor seen on the panadater with minimum amplification
and a 50 Ohm dummy load as antenna (or disconnected) should be given by the quantization noise:
NF = -6.02*8-1.76-10log(FFT bin size / 2)
but I think this formula is missing something in the case of the rtl-sdr since in the case
of r820t tuner a single IF on the I branch is sampled at 28.8 MSPS and then this is digital down
converted and decimated. So I tried to figure out the gain process as:
10log(28.8/2/3.2) ~= 6.5 dB as process gain. This seems to fit with what I see on the panadapter
of gqrx. I get about -92 dBFS with 2.4 MSPS, 0 LNA, and FFT of 8192.

Now the question for this group: there is a correction value, default offset or formula used in
gqrx code that take account of hardware implementation when displaying value on the dBFS scale?
and what are your opinion on my calculation?

There is one piece you are missing: the signal meter you are looking at does not refer to the entire input bandwidth from the hardware, but rather after the filter of the chosen demodulator. In other words, there is a second downconvert-filter-decimate step performed within gqrx, and you must account for that as well.

If I remember correctly (and I did look at the code for this once) there is no particular correction value in the meter.

Just remember that it is not dBm or any such real-world power level but dBFS — I think you've kept that straight but I'm not certain. Calibrating digital signal levels to a reference in mW or such is a whole other problem and must be done empirically rather than by calculation.

[Alexandru Csete]

On Wed, Nov 23, 2016 at 5:44 PM, Kevin Reid <kpr...@switchb.org> wrote:
>
> If I remember correctly (and I did look at the code for this once) there is
> no particular correction value in the meter.

That's correct. There is no compensation for resolution bandwidth in
the S-meter, nor the FFT plot.

Alex

[Robin Gape]

Luigi,

to answer your question one really needs the system diagram that you're attempting to quantify, and details of how any adjustments are made. In regards to SDR, then there is an issue of processing gain (the digital equivalent of Q), when signals are passed through an FFT or an FIR filter, or some other DSP process. Generally, signal processing needs more bits than any front-end A/D converter provides to allow for this.

As for quantization noise, a well-designed system will generally perform better with dithering, either added or from noise at the input (or both).

A further observation is that an A/D is also characterised by the ENOB (effective number of bits).

HTH, 73,

Robin, G8DQX

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[Luigi Tarenga]

Il giorno mercoledì 23 novembre 2016 17:44:58 UTC+1, Kevin Reid ha scritto:

There is one piece you are missing: the signal meter you are looking at does not refer to the entire input bandwidth from the hardware, but rather after the filter of the chosen demodulator. In other words, there is a second downconvert-filter-decimate step performed within gqrx, and you must account for that as well.

Kevin, I'm looking at the panadapter, not the S-meter, I think I should only care about the sample rate, decimation and FFT size.
I made further thinking about my formula and I think I missed many pieces :) I try to update what I did and discovered:

- When doing some test with 0 RF gain I'm likely hitting the bottom precision of the 8 bit samples and even if the DDC inside the rtl2832u
is contributing with some gain due to the oversampling of the ADC this gain can be lost in the math approximation of the DDC.
When using a max RF gain I effectively see different noise floor level at different sample rate.

- When computing for the DDC gain I should keep in mind that the DDC work on 2 stream (I and Q) each stream have it's quantization
noise and math approximation noise. A 2.4MSPS should be 2.4MSPS of I data and 2.4MSPS of Q data where each describe
a spectrum of 1.2Mhz that sum up to 2.4Mhz. If it was a real sampling the rate would be 4.8MSPS.
The noise of the 2 stream should add so with 2.4 MSPS I should count it twice and the oversampling gain is 10log(28.8/2/(2.4+2.4))~=4.8dB

- the overall formula for the noise floor in dbFS seen on the panadapter should become:
NF=-6.02*N-1.76-10log(28.8/4/SR)-10log(FFT/2)
where:
   - N is the bits of the ADC, 8 (not ENOB). I use 8 because I'm looking at dbFS not real world mW.
   - SR is the sample rate chosen from the gui
   - FFT is the FFT bin size

with 2.4MSPS and 8192 FFT bin size I get ~-91dbFS this value can be seen even with the LNA set to 0.
but if you want to see more gain due to oversampling and DDC decimation (not gqrx decimation) you should have the
RF gain above ~30dB or seems you are hitting the bottom 8 bit resolution or the DDC FIR filter is not as good as
the one at higher sample rate.

If I remember correctly (and I did look at the code for this once) there is no particular correction value in the meter.

Ok thanks, I needed this :)

 

Just remember that it is not dBm or any such real-world power level but dBFS — I think you've kept that straight but I'm not certain. Calibrating digital signal levels to a reference in mW or such is a whole other problem and must be done empirically rather than by calculation.

Of course, thanks.
 
I'm looking for your precious feedback!
thanks
Luigi

[Luigi Tarenga]

Il giorno mercoledì 23 novembre 2016 23:30:48 UTC+1, Robin, G8DQX ha scritto:

Generally, signal processing needs more bits than any front-end A/D converter provides to allow for this.

Yes, you are right, I was missing this point, the ADC is 8bit, the math in the DDC need more bits if you already are at the bottom end of precision.
So all this computation and rounding errors should be avoided as much as possible in the DDC and moved on host CPU. This can be archived
with decimation and higher FFT bin size.
This is what you intend right?
 

As for quantization noise, a well-designed system will generally perform better with dithering, either added or from noise at the input (or both).

I can provide some noise by raising the RF gain in the front end. right?
 

A further observation is that an A/D is also characterised by the ENOB (effective number of bits).

Ok but I'm not looking at mapping dbFS to real world dBm. Just speculating on what I see on panadapter and how those values are calculated.
 

HTH, 73,

Robin, G8DQX

73
Luigi IU2GID