Linux on soft CPU on FPGA now running, will bring Tuesday

[Brian Bartholomew]

I can now show Linux running on an FPGA. The CPU and all the rest of
the Linux system's hardware, except for RAM and sdcard disk, is
implemented inside an FPGA. http://j-core.org did all the work, I
just followed the install instructions.

The board it's running on is 3x5", cost $50 plus $14 for two-day FedEx
from India. The board has VGA but lacks an ethernet connector.
j-core.org is working on their own board, named Turtle, compatible
with the RPi form factor.

The definition of the soft CPU and other soft hardware is in the VHDL
language, plus a glue framework. It is open, but I have not built it
yet. The vendor tool to compile ("synthesize") the VHDL is free as in
beer, but not open. There is work in progress to get a free tool to
compile it. Next week I'll attempt to build everything from source:
the VHDL, the Linux kernel, the tiny Linux distribution.

(:1) / $ ls
bin dev etc home init lib mnt proc root sbin sys tmp usr
(:1) / $ ls -l
total 0
lrwxrwxrwx 1 root root 7 2016-01-11 18:38 bin -> usr/bin
drwxr-xr-x 3 root root 0 2000-01-01 00:00 dev
lrwxrwxrwx 1 root root 7 2016-01-11 18:38 etc -> usr/etc
drwxr-xr-x 2 root root 0 2016-01-11 18:38 home
lrwxrwxrwx 1 root root 13 2016-01-11 18:38 init -> /sbin/init.sh
lrwxrwxrwx 1 root root 7 2016-01-11 18:38 lib -> usr/lib
drwxr-xr-x 2 root root 0 2016-01-11 18:38 mnt
dr-xr-xr-x 35 root root 0 2000-01-01 00:00 proc
drwxr-xr-x 2 root root 0 2016-01-11 18:38 root
lrwxrwxrwx 1 root root 8 2016-01-11 18:38 sbin -> usr/sbin
dr-xr-xr-x 11 root root 0 2000-01-01 00:00 sys
drwxrwxrwt 2 root root 0 2016-01-11 18:38 tmp
drwxr-xr-x 7 root root 0 2016-01-11 18:38 usr
(:1) / $ dmesg
Linux version 4.3.0 (landley@halfbrick) (gcc version 4.2.1) #1 Mon Jan 11 12:46:56 CST 2016
Boot params:
... MOUNT_ROOT_RDONLY - 00000001
... RAMDISK_FLAGS - 00000000
... ORIG_ROOT_DEV - 00000200
... LOADER_TYPE - 00000001
... INITRD_START - 00000000
... INITRD_SIZE - 00000000
Booting machvec: 0PF_FPGA
initrd disabled
Node 0: start_pfn = 0x10000, low = 0x18000
Zone ranges:
Normal [mem 0x0000000010000000-0x0000000017ffffff]
Movable zone start for each node
Early memory node ranges
node 0: [mem 0x0000000010000000-0x0000000017ffffff]
Initmem setup node 0 [mem 0x0000000010000000-0x0000000017ffffff]
On node 0 totalpages: 32768
free_area_init_node: node 0, pgdat 102ce818, node_mem_map 103c0000
Normal zone: 256 pages used for memmap
Normal zone: 0 pages reserved
Normal zone: 32768 pages, LIFO batch:0
pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
pcpu-alloc: [0] 0
Built 1 zonelists in Zone order, mobility grouping off. Total pages: 32512
Kernel command line: console=ttyUL0 noiotrap
PID hash table entries: 512 (order: -1, 2048 bytes)
Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
Sorting __ex_table...
I-cache : n_ways=0 n_sets=0 way_incr=0
I-cache : entry_mask=0x00000000 alias_mask=0xfffff000 n_aliases=1048576
Memory: 126068K/131072K available (1993K kernel code, 154K rwdata, 472K rodata, 764K init, 191K bss, 5004K reserved, 0K cma-reserved)
virtual kernel memory layout:
fixmap : 0xdfff7000 - 0xdffff000 ( 32 kB)
vmalloc : 0xc0000000 - 0xdfff5000 ( 511 MB)
lowmem : 0x10000000 - 0x18000000 ( 128 MB) (cached)
.init : 0x102d0000 - 0x1038f000 ( 764 kB)
.data : 0x1023244c - 0x102cf060 ( 627 kB)
.text : 0x1003f000 - 0x1023244c (1997 kB)
SLUB: HWalign=16, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
NR_IRQS:512
0PF FPGA interrupt controller...
arch_clk_init(): 0PF Clock init...
Console: colour dummy device 80x25
Calibrating delay loop (skipped)... 32.00 BogoMIPS PRESET (lpj=160000)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
CPU: SH2J-0PF
devtmpfs: initialized
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
NET: Registered protocol family 16
shj_devices_setup(): registering device resources
Register UARTLITE resources 0
Register UARTLITE resources 1
Register UARTLITE resources 2
0PF Machine setup...
EMAC prio is: 7000078
0PF Machine setup done.
SCSI subsystem initialized
NET: Registered protocol family 2
TCP established hash table entries: 1024 (order: 0, 4096 bytes)
TCP bind hash table entries: 1024 (order: 0, 4096 bytes)
TCP: Hash tables configured (established 1024 bind 1024)
UDP hash table entries: 256 (order: 0, 4096 bytes)
UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
NET: Registered protocol family 1
futex hash table entries: 256 (order: -1, 3072 bytes)
squashfs: version 4.0 (2009/01/31) Phillip Lougher
9p: Installing v9fs 9p2000 file system support
io scheduler noop registered (default)
uartlite.0: ttyUL0 at MMIO 0xabcd0100 (irq = 18, base_baud = 0) is a uartlite
console [ttyUL0] enabled
uartlite.1: ttyUL1 at MMIO 0xabcd0300 (irq = 23, base_baud = 0) is a uartlite
uartlite.2: ttyUL2 at MMIO 0xabcd0400 (irq = 19, base_baud = 0) is a uartlite
loop: module loaded
NET: Registered protocol family 17
9pnet: Installing 9P2000 support
hctosys: unable to open rtc device (rtc0)
Freeing unused kernel memory: 764K (102d0000 - 1038f000)
(:1) / $ cat /proc/cpuinfo
machine : 0PF_FPGA
processor : 0
cpu family : sh2eb
cpu type : SH2J-0PF
cut : 0.0
cpu flags : none
cache type : unified
cache size : 0KiB (0-way)
address sizes : 32 bits physical
bogomips : 32.00
(:1) / $ cat /proc/meminfo
MemTotal: 126832 kB
MemFree: 121940 kB
MemAvailable: 121156 kB
Buffers: 0 kB
Cached: 1824 kB
SwapCached: 0 kB
Active: 784 kB
Inactive: 1008 kB
Active(anon): 0 kB
Inactive(anon): 0 kB
Active(file): 784 kB
Inactive(file): 1008 kB
Unevictable: 0 kB
Mlocked: 0 kB
MmapCopy: 1304 kB
SwapTotal: 0 kB
SwapFree: 0 kB
Dirty: 0 kB
Writeback: 0 kB
AnonPages: 0 kB
Mapped: 0 kB
Shmem: 0 kB
Slab: 1228 kB
SReclaimable: 180 kB
SUnreclaim: 1048 kB
KernelStack: 200 kB
PageTables: 0 kB
Quicklists: 0 kB
NFS_Unstable: 0 kB
Bounce: 0 kB
WritebackTmp: 0 kB
CommitLimit: 63416 kB
Committed_AS: 0 kB
VmallocTotal: 0 kB
VmallocUsed: 0 kB
VmallocChunk: 0 kB
(:1) / $

[Brian Bartholomew]

I have compiled the VHDL of the j-core computer. This is not to say I
have built everything with audited tools. The trust stack is not
turtles all the way down, the stack is finite. But there is a stack.

Reflections on Trusting Trust
and countermeasures to it

http://dl.acm.org/citation.cfm?id=358210
http://c2.com/cgi/wiki?TheKenThompsonHack
https://www.schneier.com/blog/archives/2006/01/countering_trus.html
http://www.dwheeler.com/trusting-trust/
http://bellard.org/tcc/

[Brian Bartholomew]

http://temlib.org/site/?page_id=297

Here is another, entirely separate computer-in-FPGA project, this one
implementing a SPARCstation 5. Link has screenshots running GUIs of:

Linux RedHat 4.2
Linux Debian 4.0
Linux Aurora 1.0
NetBSD 5.1
OpenBSD 5.3
SunOS 4.1.4 / SunView
SunOS 4.1.4 / OpenLook
NextStep 3.3

I built and ran gentoo Linux on SPARCstation 5 for a UF department's desktops.

Earlier today I learned someone has built a thing I've been wanting,
Lisp running on top of the perl backend. It's a variant of Clojure,
which reins in the wild and freewheeling use of mutators.

What else would I wish for? Lots of cheap little sensor computers
running the Plan 9 filesystem over IPv6. (j-core seems to be
targeting that already)

We're living in the science fiction future, today. If I keep googling
maybe I'll find that elusive flying car, or the shuttle to Mars...

Brian

[GRB352]

I did a search for 9p and arduino to see if it would be easy to put on ESP8266, but all I found is NinePea, and it looks a little underdeveloped.

[GRB352]

I saw this article about a combo arduino/FPGA board. 
https://folknologylabs.wordpress.com/2016/07/21/a-perfect-storm/

while this board isn't out, there are similar ones out there in the wild. As I am getting somewhat familiar with arduino I would feel more comfortable inching my way to FPGA  by bringing in a couple FPGA functions into a mostly arduino project. Is that practical or just silly?  

[Daniel Crews]

I'm not sure. For most things you want to do with an fpga, hamstringing your self with limited overall design and board design feels point less... may as well just learn to program your arduino with C or assembly. But I guess it might be an effective way to learn basics. Personally, even if we accept not trying to build a "sensible" system in order to learn, I think it's best to leave the Arduino out. Learning the vagaries of two systems at the same time will probably result in lots of fried chips.

As regards that project at first it appeared quite promising, but I was turned off by what appeared to be blatant astroturfing in the hackernews thread for it and a sneaking suspicion that their suggested price point is a fantasy. Also while we have an open tool chain for the ice40 fpgas now, I find myself far more interested in completing the work to get a similar tool chain for the Spartan6 line, at least for more audacious designs. This board feels like it falls in between the cracks to me. Too much for the one and too little for the other.

--
You received this message because you are subscribed to the Google Groups "Gainesville Hackerspace" group.
To unsubscribe from this group and stop receiving emails from it, send an email to gainesville-hackerspace+unsub...@googlegroups.com.
To post to this group, send email to gainesville-hackerspace@googlegroups.com.
To view this discussion on the web, visit https://groups.google.com/d/msgid/gainesville-hackerspace/18d9553d-44eb-49a8-b1d9-32f097fc0244%40googlegroups.com.

For more options, visit https://groups.google.com/d/optout.

--

Fin

[Brian Bartholomew]

There were two followup posts, one of which showed a breakdown of how
they were going to make the $30 price. I'm don't know how that
manufacturing works enough to tell if it's believable.

In general I suggest picking whatever hardware board is best supported
by the software you plan to use. Is this motion control for a delta
3D printer, a robot, or something else? Do you want to run an
existing printer firmware? Are these easy to port to a new board?

If some stuff will be happening in Arduino and some in FPGA, then
you're doing parallel processing. One important number is how often
the two pieces need to talk. 100 times a second is easy to arrange, 1
million times a second is hard.

Recently I saw a CNC article where Windows computed a toolpath in the
usual distracted and non-real-time fashion, and the FPGA generated the
acceleration ramps and clocked out step and direction pulses with
precise timing. As that article pointed out, time jitter in the
pulses directly produces unwanted jaggies in the cut line. This was a
good design in part because the communication from CPU to FPGA was
slow and thus easy to do. The FPGA expanded the CPU's direction
signals into faster, pickier pulses.

I can't recommend the Lattice iCEstick, it's too small. It has about
1,000 lookup table units, and my button debounce + 7 segment adds two
numbers thing takes up about 800. The perfect storm board picked a
4,000 unit Lattice part.

Brian