How to design a fast "Floting Counter"

[Tibi]

Hello,

I am supposed to design a counter having floating lenght, the main
idea is to implement it to put the MSB always in the first position
and as soon as it is required the length of the counter increased. In
this case the counter have to be very fast.

Something like this:
1
10
11
100...
without leading zeros

If you have any idea ,please, let me know.

Thanks

[Ray Andraka]

if you look at the bit patterns, it will give you a clue:

the msb is always '1' except on the first clock (the zero count), so that one is
easy.
The next bit down goes in the sequence - 0 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0
0 0 1 1 1 1 1 1 1 1
so you'll need to design a state machine to do that bit. The remaining bits are
delayed copies of that second bit: 3rd bit is 2nd delayed by 2, next is delayed
by 4 more, next by 8 more etc.

That should be enough of a clue to get you started. You'll probably also want
an exponent. That is a binary count that gets incremented on each 1 to 0
transition from the next to MSB state machine.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email r...@andraka.com
http://www.andraka.com

[Tibi]

Thank you for your hints, however, I don't really know how to
implement it. It is true that the sequence is shifted to the following
bit and delayed by 2, 4, 8 and so on, but the bit sequence also
changes. Every time it is given to a new bit the sub parts of it are
doubled:

1 11 1111 11111111 11111111111111111...
01 0011 00001111 00000000111111110...
0101 00110011 00001111000011110...
01010101 00110011001100110...
01010101010101010...
0...

and so on. I hope it is somewhat readable.

If you could provide me some source code it would me really helpful.

Thank you

Ray Andraka <r...@andraka.com> wrote in message news:<3B1106DC...@andraka.com>...

[Tibi]

Hi,

I tried to do something, however, it doesn't seem to be very
efficient.

library ieee; use ieee.std_logic_1164.all;
library ieee; use ieee.std_logic_arith.all;
library ieee; use ieee.std_logic_unsigned.all;

entity fcnt is
generic(n: integer :=16); --lenght of the counter
port(
clk : in std_ulogic;
rst : in std_ulogic;
start : in std_ulogic;
cnt_out : buffer unsigned(n-1 DOWNTO 0)
);
end fcnt;

architecture fcnt_a of fcnt is
begin
process(clk,rst)

variable cnt_length: integer range n-1 downto 0;
variable value: unsigned (n-1 downto 0);
-- constant ones: unsigned (n-1 downto 0) :=(others => '1');

begin

if (rst = '1') then
cnt_out<=(others => '0');
value:=(others => '0');
cnt_length:=1;
elsif ((clk'event and clk = '1') ) then

-- if value(cnt_length downto 0)= ones(cnt_length downto 0)
then --if the floating value is full of 0 then

if value(0)='1' then --looks for the first 0 from the right
for i in 1 to cnt_length loop
if i=cnt_length and value(cnt_length-1)='1' then
cnt_length:=cnt_length+1; --increment the length of it
value(cnt_length-1):= '1'; --and make it in 100..00 form
value(cnt_length-2 downto 0):= (others=>'0');
exit;
elsif
value(i-1)='0' then
value(i-1):='1'; --changes the found 0 to one and put
0s to the left side of it
value(i-2 downto 0):=(others=>'0');
exit;
end if;
end loop;
else value(0):='1'; --toggles the first bit
end if;

end if;

cnt_out<=value;
end process;
end fcnt_a;

If you have any suggestion how to make it good, Please let me know!

Thanks

ti...@eudoramail.com (Tibi) wrote in message news:<186b3684.0106...@posting.google.com>...