CPU design with Verilog

[sorressean]

Hello all,
I am a totally blind student and am in a computer architecture class. For our end-of-semester project, we are to design a processor of our choice.
I have a couple of questions. First, the students are using logisym which is not accessible with a screen reader. Verilog was the only solution we found that allows me to actually participate in this project.
I am using Icarus Verilog as my compiler.
I have a few questions which I hope will get me going on the right path.
1. is there a good reference for the version of Verilog that Icarus uses?
2. What might be the best way to implement an ALU? My solution was a muxer, but I'm a bit confused here as to how this is implemented. In the least, I'll need the instructions and the registers. How does the math take place once you select the operation with your muxer?
3. How would one simulate voltage for clock cycles?
4. How do you simulate memory to be attached to the processor?
5. Is there an implimentation of registers that I can work with, or is there a good way to create my own?

My biggest and overall issue is the design of this entire thing by itself. From what I can tell, each individual component will be a module in and of itself. So, the registers will be an individual module as will the ALU. So for the main cPU, I'll need to declare the registers as well as the ALU inside the CPU module. Given this:
1. Is there a way to declare an array or group of modules?
2. If i have my ALU module declared on the CPU module, how will the ALU access registers? Will those have to be wired individually?

I'm sorry for what is probably a misguided and confusing message. I understand the basics, but I am a bit confused. Any suggestions and ideas would be amazing.

Thanks,

[rickman]

On 11/17/2014 1:06 AM, sorressean wrote:
> Hello all,
> I am a totally blind student and am in a computer architecture class. For our end-of-semester project, we are to design a processor of our choice.

I have to say I'm impressed. I have wondered if I would be able to
continue doing this sort of work if I were blind and it seems like it
would certainly be a lot harder.

> I have a couple of questions. First, the students are using logisym which is not accessible with a screen reader. Verilog was the only solution we found that allows me to actually participate in this project.
> I am using Icarus Verilog as my compiler.
> I have a few questions which I hope will get me going on the right path.
> 1. is there a good reference for the version of Verilog that Icarus uses?

I don't think Verilog has "versions" per-se other than the various,
mostly compatible updates. Normally using an older version of Verilog
in your code is 100% compatible with more current tools. The compiler
documentation should tell you which version of Verilog is supported.

> 2. What might be the best way to implement an ALU? My solution was a muxer, but I'm a bit confused here as to how this is implemented. In the least, I'll need the instructions and the registers. How does the math take place once you select the operation with your muxer?

I'm not at all sure what you mean by a "muxer". If you are working in
an HDL people typically just code the logic and let the tool decide how
to implement it in the technology. To get into the details of how that
might best be controlled would depend on the device you are implementing
it on.

> 3. How would one simulate voltage for clock cycles?

When working in an HDL it is not normally used for anything other than
logic simulation. Once as part of a test bench I included the equations
for an RC filter external to the part to support an ADC design. I put
them in a process that ran on every clock cycle which was good enough
since the RC constant was long compared to the clock cycle.

> 4. How do you simulate memory to be attached to the processor?

You just describe it in your test bench like any other memory.

> 5. Is there an implimentation of registers that I can work with, or is there a good way to create my own?

I'm not sure what this means. Registers are usually just a very small
block of memory in terms of the HDL code. Sometimes you want them to
have two or even more ports which is not too hard to do in a sequential
process. You just add more than one address and controls all in the
same process.

> My biggest and overall issue is the design of this entire thing by itself. From what I can tell, each individual component will be a module in and of itself. So, the registers will be an individual module as will the ALU. So for the main cPU, I'll need to declare the registers as well as the ALU inside the CPU module. Given this:
> 1. Is there a way to declare an array or group of modules?

I'm not sure what this is asking.

> 2. If i have my ALU module declared on the CPU module, how will the ALU access registers? Will those have to be wired individually?

Yes, each module will have inputs and outputs which at the CPU level
will be wired together... one of the down sides of using modules. I'm
not sure modules are required for a simple CPU. If your instruction set
is not specified, take a look at some stack machines. For FPGAs and the
like they are very small and efficient designs and easy to code.

> I'm sorry for what is probably a misguided and confusing message. I understand the basics, but I am a bit confused. Any suggestions and ideas would be amazing.

Trust me, for a newbie these are very good questions. Many times people
are either asking for someone to do their work or they want to know how
long is a piece of string.

--

Rick

[GaborSzakacs]

sorressean wrote:
> Hello all,
> I am a totally blind student and am in a computer architecture class. For our end-of-semester project, we are to design a processor of our choice.
> I have a couple of questions. First, the students are using logisym which is not accessible with a screen reader. Verilog was the only solution we found that allows me to actually participate in this project.
> I am using Icarus Verilog as my compiler.
> I have a few questions which I hope will get me going on the right path.
> 1. is there a good reference for the version of Verilog that Icarus uses?

My favorite reference is the Doulos Golden Reference, which includes
Verilog 95 as well as Verilog 2001. I used Thomas and Moorby's book
when learning Verilog 95. That book is good to get started even if
it doesn't cover Verilog 2001.

> 2. What might be the best way to implement an ALU? My solution was a muxer, but I'm a bit confused here as to how this is implemented. In the least, I'll need the instructions and the registers. How does the math take place once you select the operation with your muxer?

I assume you mean multiplexer. This is essentially correct. At the
top level, the instruction selects the output of the ALU from the
possible functions like add, subtract, and, or, etc. Of course you
need to implement each of these functions to provide the data inputs
to the multiplexer.

> 3. How would one simulate voltage for clock cycles?

Not sure what you mean by voltage. The Verilog language treats
logic as levels of 1 or 0 regardless of the actual voltage used
to implement that logic. If you mean how to drive a clock into
your circuit for simulation, that is fairly easy using a simple
loop with time delay in the test bench as in:

reg clock = 0;
always clock = #5 !clock;

> 4. How do you simulate memory to be attached to the processor?

Again this depends on what sort of memory. If the memory will be
some off-the shelf chip, you might find a Verilog simulation model
at the chip manufacturer's website. If it's just simple static RAM
you can infer that in your test bench using an array like:

reg [7:0] memory [0:65535]; // 64 Kbytes of 8-bit wide memory

> 5. Is there an implimentation of registers that I can work with, or is there a good way to create my own?
>

The CPU's internal registers can be just a loose bunch of Verilog
regs like:

reg [7:0] A_reg;
reg [7:0] B_reg;
. . .

or you can use an array of registers, which makes it simpler to create
code that selects a register based on some bits of the instruction like:

reg [7:0] Registers [0:15]; // 15 8-bit registers you can address using
4 bits

> My biggest and overall issue is the design of this entire thing by itself. From what I can tell, each individual component will be a module in and of itself. So, the registers will be an individual module as will the ALU. So for the main cPU, I'll need to declare the registers as well as the ALU inside the CPU module. Given this:
> 1. Is there a way to declare an array or group of modules?

Verilog since Verilog 95 has the ability to declare an array of
instances. Thus if you had a bit-slice architecture you could
use an array of instances to generate a group of these slices
organized as a larger (wider) ALU.

> 2. If i have my ALU module declared on the CPU module, how will the ALU access registers? Will those have to be wired individually?
>

As I pointed out above, you can use individual registers or a
register "file". The latter can be addressed like memory using
bits from the instuction code.

> I'm sorry for what is probably a misguided and confusing message. I understand the basics, but I am a bit confused. Any suggestions and ideas would be amazing.
>

Not at all. You have to start somewhere, and your questions point to
some thought about the process. I'd suggest trying to find a user guide
for a simple early 8-bit CPU like the Motorola 6800. This might provide
more insight.

> Thanks,

You're welcome.

--
Gabor