Is System verilog array of interfaces allowed?

[vijay]

I have a requirement to design a module with a customizable number of
submodules. I was thinking of using an array of interfaces at the
toplevel and for-generate to connect them to the submodules; with the
number of submodules passed as a parameter, while checking the
validity of the code I am getting compilation error from dc.
e.g. The code below compiles fine. but if we uncomment the first line
we get an error of " The name 'enc' is not a modport of the interface
instance actually provided on port 'ekIfc[0]'."

Is there some way of achieving the intended result?
//****************** Start Code ********************************
//`define array
`ifndef array
`define index
`define parindex
`define forloopbegin
`define forloopend
`else
`define index [i]
`define parindex [numInstance]
`define forloopbegin for(i=0;i<numInstance;i=i+1) begin
`define forloopend end
`endif
interface ioIfc;
logic encryptedData;
logic decryptedData;
modport enc(input decryptedData,output encryptedData);
modport dec(output decryptedData,input encryptedData);
endinterface

module ek(ioIfc.enc enc);
endmodule

module dk(ioIfc.dec dec);
endmodule

module top#(numInstance=5)(
ioIfc.enc ekIfc `parindex,
ioIfc.dec dkIfc `parindex
);
genvar i;
generate
`forloopbegin
ek ek(.enc(ekIfc`index));
dk dk(.dec(dkIfc`index));
`forloopend
endgenerate
endmodule
//****************** End Code ********************************

[Jonathan Bromley]

On Jun 24, 12:22 pm, vijay wrote:
> The code below compiles fine. but if we uncomment the first line
> we get an error of " The name 'enc' is not a modport of the interface
> instance actually provided on port 'ekIfc[0]'."

Two questions:

1) did you get this to compile and elaborate in a simulator?

2) Although your definition of `parindex as [numInstance]
is legal according to the language spec, I wonder if perhaps
DC is not accepting the shorthand unpacked_dimension? Did
you also try [0:numInstance-1] as the instance dimension?

But I agree that your code looks OK.

I have had endless trouble with attempting to use
interfaces in generate loops and instance arrays.
It doesn't surprise me if there are some other tool
wrinkles with what you are trying to do.

Good luck, and please let us know how you get on!
--
Jonathan Bromley

[vijay]

On Jun 25, 2:09 pm, Jonathan Bromley <s...@oxfordbromley.plus.com>
wrote:

> On Jun 24, 12:22 pm, vijay wrote:
>
> > The code below compiles fine. but if we uncomment the first line
> > we get an error of " The name 'enc' is not a modport of the interface
> > instance actually provided on port 'ekIfc[0]'."
>
> Two questions:
>
> 1) did you get this to compile and elaborate in a simulator?
>

The simulator (vcs) required some changes to the code (new code at the
end of this mail) in order to compile without the "`define array"
directive. But with the `define directive it gives rise to a new
error. It somehow infers that ek is a toplevel module and errors out
with
-----------------------Begin Error message
Parsing design file 'testenc.sv'
Top Level Modules:
topwrap
ek

Error-[SV-UIP] Unconnected interface port
testenc.sv, 40
"enc"
The port 'enc' of top-level module 'ek' whose type is interface
'ioIfc' is
left unconnected. Interface ports must be connected.

-----------------------End Error message

> 2) Although your definition of `parindex as [numInstance]
> is legal according to the language spec, I wonder if perhaps
> DC is not accepting the shorthand unpacked_dimension? Did
> you also try [0:numInstance-1] as the instance dimension?

Yes. Without success...
Also if I declare an unused interface array in the portlist DC does
not complain. it seems to have issues only while connecting it using
for generate construct.

>
> But I agree that your code looks OK.
>
> I have had endless trouble with attempting to use
> interfaces in generate loops and instance arrays.
> It doesn't surprise me if there are some other tool
> wrinkles with what you are trying to do.

My usage of interfaces for the past three years was with BSV
(Bluespec's dialect of systemverilog) which has unfortunately raised
my expectations from what could be done with vanilla SystemVerilog :(

>
> Good luck, and please let us know how you get on!

Thanks, My current plan is to use either ep3 or template toolkit in
case I am not getting the for-generate combination to work.
REgards
Vijay
> --
> Jonathan Bromley

--------------------------Start New Version of code

//`define array
`ifndef array
`define index
`define parindex
`define forloopbegin
`define forloopend
`else
`define index [i]

`define parindex [0:numInstance-1]

`define forloopbegin for(i=0;i<numInstance;i=i+1) begin:
`define forloopend end
`endif
interface ioIfc;
logic encryptedData;
logic decryptedData;
modport enc(input decryptedData,output encryptedData);
modport dec(output decryptedData,input encryptedData);
endinterface

module topwrap();
ioIfc test();
top top(test.enc,test.dec);
endmodule

module top#(numInstance=5)(
ioIfc.enc ekIfc `parindex,
ioIfc.dec dkIfc `parindex

,ioIfc.dec dkIfcTest [numInstance]

);
genvar i;
generate
`forloopbegin

ek ek1(.enc(ekIfc`index));

dk dk(.dec(dkIfc`index));
`forloopend
endgenerate
endmodule

module ek (ioIfc.enc enc);
always @(*)begin
enc.encryptedData=enc.decryptedData;
end
endmodule

module dk (ioIfc.dec dec);
assign dec.decryptedData=dec.encryptedData;
endmodule

--------------------------End New Version of code