Verilog format, which include sequential circuits and/or memory
part ?
Sincerely ,
Jih-Jeen Chen
http://www.prep.org/testbnch/synth.htm
Benchmarks include a bit slice, R4000 RISC machine, Basic multiplier etc etc.
--
Ruth Faulkner
Design Engineer, SoCDT UK
Email: Ruth_F...@email.mot.com
Tel: +44 (0)1606 815436
Visit
http://www.isdmag.com/edabenchmark/
These are fairly large benchmark designs.
Rajesh Bawankule
Email: raje...@hotmail.com
Verilog Page: http://www.angelfire.com/in/rajesh52/verilog.html
Verilog FAQ : http://www.angelfire.com/in/verilogfaq/
In article <7be34i$mlo$1...@ccnews.ncku.edu.tw>,
-----------== Posted via Deja News, The Discussion Network ==----------
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Sun has announced that source code for the picoJava and Sparc
processor cores will be made available under the Community
Source Licensing agreement. The picoJava core source files should
be posted on the web sometime this month. The sources include design
files (in Verilog) for the complete picoJava core, system simulation
environment, tests, etc. The verilog source files for the picoJava
design total approximately 75,000 lines of source code.
This is a production quality core and test environment, which was available
till now only to picoJava licensees, but is now being released to the
general public (and is free for non-commerical use)
Feel free to use this design for benchmarking or testing EDA
tools. See http://www.sun.com/microelectronics/communitysource
for more info on picoJava source code availability and Sun's community
source licensing principles.
-s
--
Sudheendra Hangal
Sun Microsystems