Can ncsim handle negative holdtimes?

[Stefan Neft]

Hi all,

during sdf-simulation with ncsim I´ve recognized that the negative holdtimes
in the sdf-files has been ignored.
So my question:
Can ncsim handle negative holdtimes?
If yes, how I can I force ncsim to use it?

Thanks in advance
Stefan

[Martyn Pollard]

"Stefan Neft" <stefa...@philips.com> wrote in message
news:3db40c81$0$223$4d4e...@businessnews.de.uu.net...

Hi, Its hard to give a complete answer without seeing the actual sdf. You
can turn on ntc_verbose to ncelab to see the actual values being calculated.

I would recommend asking your Applications Engineer to install LDV41p2 for
you. That version has some improvements in calculating negative timing
values.

Martyn

--
Martyn Pollard

NCSim - High Performance VHDL/Verilog Simulation
NCVHDL, NCVerilog, Verification Cockpit
Cadence Design Systems. http://www.cadence.com/ncsim

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[eda_dude]

> during sdf-simulation with ncsim I´ve recognized that the negative holdtimes
> in the sdf-files has been ignored.
> So my question:
> Can ncsim handle negative holdtimes?
> If yes, how I can I force ncsim to use it?

If you are running 'gate-level' simulations using a foundry vendor's
Verilog library, you should know that some vendors' libraries don't
support negative-annotation checking. Ask your vendor about this.

[Arturi]

Hello Martyn,
I am elaborating a design using the ntc_verbose option and I get a lot
of messages like:

ntc is modifying the data limit from -40000 to 0 at location 5552:
./verilog/fflop_lib.v

What do these messages mean? Are the holdtimes being set to ZERO? If
yes, what could be causing it? I am also using -NEG_TCHK to elaborate
the design.
The ncelab verison is v04.00.(s003)
Any hint or help will be greatly appreciated.
Thanks in advance,

"Martyn Pollard" <m...@abccadence.com> wrote in message news:<3db4...@news.cadence.com>...

[Martyn Pollard]

> ntc is modifying the data limit from -40000 to 0 at location 5552:
> ./verilog/fflop_lib.v
>
> What do these messages mean? Are the holdtimes being set to ZERO? If
> yes, what could be causing it? I am also using -NEG_TCHK to elaborate
> the design.

The most likely cause is that you have non-overlapping windows for negative
setuphold and the simulator is setting some limits to zero, thus forcing the
convergence. This was the case with version 4.0 of NCVerilog.

Here is an example of non-converging window for a FlipFlop

$setuphold(posedge ck, posedge d, 12,-9,,,,delayed_ck,delayed_d)
$setuphold(posedge ck, negedge d, 5, -4,,,,delayed_ck,delayed_d)

In this case, -9 and -4 would be set to zero. I think thats happening in
your case, although -40000 seems a very large value. What technology library
are you using?

> The ncelab verison is v04.00.(s003)

Try this before you take up too much time debugging. Download v04.01p2, from
sourcelink.cadence.com ->software update. You'll also need to request a new
license. This version of the software will be able to simulate without
NCVerilog being overly pessimistic and setting the limits to zero.

If you still have a problem please call the Cadence helpdesk so they can
help you further.

Martyn

[Arturi]

Hello Martyn!
Thanks for your support.
I was also wondering why such high values, the thing is I'm using CMOS
.50 library and these values can't be found neither in the lib file
nor in the SDF file. I wonder where ncelab take them from.
I guess the SDF file is not being properly compiled by ncsdfc. Did you
hear anything about incompatibility with SDF files generated with
PEARL?? The strange thing is that I don't get any error message in the
ncsdfc log file.
When elaborating the design I get the following warnings:

ncelab: *W,SDFRDE: Read error for default code, skipping annotation of
./SDF/top.ncsdf.
ncelab: *W,SDFRDE: Read error for default code, skipping annotation of
./SDF/top.ncsdf.

No chance to find where they come from, so I tried to use the version
4.1 and when elaborating the design I got the following:

ncelab: *W,SDFUXC: Unexpected code found in compiled SDF file:
./SDF/top.ncsdf (148).
ncelab: *W,SDFINF: Instance vfl not found at scope level
core_bst_i1.core_i1 <./SDF/top.sdf, line 554007>.
ncelab: *W,SDFINF: Instance i_401799 not found at scope level
core_bst_i1.core_i1 <./SDF/top.sdf, line 553860>.

The last two warnings I tried to check, but the lines referred have no
signs of the instances mentioned. More strage is the fact that nowhere
in the SDF file I can find the instances vfl and i_401799 direct under
core_i1. They are instanciated deeper in the hierarchy. How does
ncelab comes up with this?
Maybe you can help me out with this too.
Regards
Arthur
"Martyn Pollard" <m...@abccadence.com> wrote in message news:<3dd96ff8$1...@news.cadence.com>...

[Martyn Pollard]

> No chance to find where they come from, so I tried to use the version
> 4.1 and when elaborating the design I got the following:
>
> ncelab: *W,SDFUXC: Unexpected code found in compiled SDF file:
> ./SDF/top.ncsdf (148).
> ncelab: *W,SDFINF: Instance vfl not found at scope level
> core_bst_i1.core_i1 <./SDF/top.sdf, line 554007>.
> ncelab: *W,SDFINF: Instance i_401799 not found at scope level
> core_bst_i1.core_i1 <./SDF/top.sdf, line 553860>.
>
> The last two warnings I tried to check, but the lines referred have no
> signs of the instances mentioned. More strage is the fact that nowhere
> in the SDF file I can find the instances vfl and i_401799 direct under
> core_i1. They are instanciated deeper in the hierarchy. How does
> ncelab comes up with this?
> Maybe you can help me out with this too.
> Regards
> Arthur

Hi. Thanks for trying the 41 version. This looks like an error in the
ncelab tool. Can you please file a bug report with the Cadence helpdesk so
that they can help you isolate the problem. I can't really give you much
further guidance without seeing your SDF file. You can find your local
support contacts on this page. http://www.cadence.com/support/index.html

Thanks,