NCSIM - Simulation Error

[Kartik Vaidyanathan]

Hi I am learning to use the NCSIM simulator to simulate some verilog
code. Its a simple 4:1 multiplexer to make things simple.

I go through the following steps without errors
1. ncvlog design.v
2. ncvlog tb.v
3. ncelab worklib.design:module (using modules in the design)
4. ncelab worklib.tb:module
5. ncsim -gui tb

NCSim opens up ok and the i select signals in the testbench. When i
hit the waveform button on the corner of the window i get the
following ERROR

SimControl Alert
WARNING : Skipping 7 Objects due to no read Access

Has anybody faced this problem before. Any help would be appreciated!!

thanks
Kartik

[Martyn Pollard]

"Kartik Vaidyanathan" <vaid...@egr.msu.edu> wrote in message
news:173cf24b.02082...@posting.google.com...

When you compile (ncvlog/ncvhdl) use the -linedebug switch to allow you to
probe signals. This will turn on full debugging access to the file being
compiled.

Make sure you remove the switch when you have debugged a particular block in
the design - the simulation will run a lot faster!

Martyn

--
Martyn Pollard

NCSim - High Performance VHDL/Verilog Simulation
NCVHDL, NCVerilog, Verification Cockpit
Cadence Design Systems. http://www.cadence.com/ncsim

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[Srinivasan Venkataramanan]

Hi,
Other option could be to specify ACCESS during ncelab, i.e.

ncelab -access +RWC tb

(BTW, you don't need to do ncelab on design & tb separately, one ncelab on
top most level(s) would do). Again, this would slow up the simulations.

HTH,
Srinivasan

--
Srinivasan Venkataramanan
ASIC Design Engineer
Software & Silicon Systems India Pvt Ltd. - an Intel company
Bangalore, India

I don't speak for Intel
"Martyn Pollard" <m...@abccadence.com> wrote in message
news:3d6e594f$1...@news.cadence.com...

[Srinivasan Venkataramanan]

Hi,
Other option could be to specify ACCESS during ncelab, i.e.

ncelab -access +RWC tb

(BTW, you don't need to do ncelab on design & tb separately, one ncelab on
top most level(s) would do). Again, this would slow up the simulations.

HTH,
Srinivasan

--
Srinivasan Venkataramanan
ASIC Design Engineer
Software & Silicon Systems India Pvt Ltd. - an Intel company
Bangalore, India

I don't speak for Intel
"Martyn Pollard" <m...@abccadence.com> wrote in message
news:3d6e594f$1...@news.cadence.com...

[Martyn Pollard]

"Srinivasan Venkataramanan" <srini...@siliconsystems.no_spam.co.in> wrote
in message news:aknhqq$k...@news.or.intel.com...

> Hi,
> Other option could be to specify ACCESS during ncelab, i.e.
>
> ncelab -access +RWC tb

Srini, Its good to know about this advanced option, but it could cause
confusion if new users don't know the difference between -linedebug
and -access.

* -linedebug ; turns on access +RWC, turns on line breakpoint debugging.
* -access +RWC ; turns on read(probe objects), turns on write(force
objects), turns on connectivity(signal flow browser, driver values).
There is a priority ordering with -access, so if you turn on W, you get RW.
If you turn on C you get RWC.

-access is a very big hit to simulation speed. If you really want to get
advanced and control which parts of you design have access there is an
automatic way to do it; ncelab -genafile <afile>. Now run the simulation.
When the simulation is completed, it will produce the <afile> which can be
read back into the elaborator; ncelab -afile <afile>. Now when you run the
simualation the second time only the parts of the design which were accessed
will have the required visibility. This gives the same functionality as the
first run, but simulation speed will scale up depending on the size of the
design. The <afile> is ascii, so once it creates the default access file,
you can go in and modify it as desired.

Now, if you are running large gate level with sdf simulations, you can do a
similar thing with the timing in the design. Look in the docs under -tfile
(timing file).

[char...@precise-itc.com]

Thanks! This is what I needed.