TSMC tech RF_NMOS layout problem in LVS (conflicting connections stamping layer sub)

[Sarsam]

I have drawn a simple NMOS_RF in schematic (I'm using TSMC 0.18 um process).

All the NMOS_RF's terminals are connected to the appropriate ports named myG (for gate), myS, myD, myB (for body).

Then in the layout window, I generated the layout. all the pins are connected. when I checked the LVS, I got this error:

LVS report:
Conflicting connections STAMPing layer sub:2 by layer psub.

Location: (2.900,6.500)
Nets: myB 7


in the comparisons results tab:

Nets,instances and ports are equal in the layout and

schematic
Nets : 4L, 4S
Instances : 1L, 1S
Ports : 4L, 4S

But I have to discrepancies:
Incorrect instances:
Discrepancy #1:
Layout Name source name
0(17.340,17.500) nmos_rf **missing instance**

Discrepancy #2:
Layout Name source name
**missing instance** M0 MN(NMOS_RF)


I can share the images of schematic,layout and discrepancies, if it is required.

How can I solve this discrepancies?

Kind regards,

Sarsam