Where do I get LEF/DEF ?
Anil Dalwani
I'm a new user of Silicon Ensemble. I suppose I need LEF and DEF files
to use the tool. But I dont know where to get these files from. I have
an account with MOSIS and have to use 0.18 process technology ( I have
been using this with virtuoso tools ). Could anyone please tell me
what do these files do and where do I get these from ? I tried to look
into MOSIS webpage but with no luck.
Thanks in advance,
-Anil
Caillet
"Anil Dalwani" <adal...@binghamton.edu> wrote in message
news:c4ecc514.02101...@posting.google.com...
a first lef file containt the description of the technologie, layer, type,
via type...
a second lef file containt the description of the cells, size, position of
the pin, obsctruction, type of pin....
a others lef file for the pad, memories...
a def file containt your netlist of you design, the floorplan (size,
placement of memories, rows...), Power nets draw...
Normaly the lef files are give with your fonder, look at Artisan for
exemple.
The def file is generate with a tools, like synopsys or cadence.
Régis
Cadence User anti-spam
> I'm a new user of Silicon Ensemble. I suppose I need LEF and DEF files
> to use the tool. But I dont know where to get these files from. I have
> an account with MOSIS and have to use 0.18 process technology ( I have
Basically, you read in the LEF (block outline, pins, keep outs, etc.);
and you generate the DEF (block location, block-to-block routing, etc.).
If you're using standard cells or RF/Analog/Mixed-Signal blocks from a
library vendor, then that supplier of the standard cells typically provides
the LEF for each block (aka macro), and the technology LEF for the process.
If you're generating memory blocks using a standard-cell library,
then part of that generation output will be a LEF macro text abstract.
If you're creating the blocks (RF/Analog/Mixed-Signal/Digital/Memory)
yourself, then you can use the Cadence(r) Abstract Generator supplied with
Silicon Ensemble(tm) to generate technology LEF, geometry LEF, and/or antenna
LEF (there are many other methods, but, this is the method I recommend).
To go from DFII to Silicon Ensemble, the best approach, IMHO, is:
o In Cadence Design Framework II, generate GDSII & a Verilog pin list:
CIW: File->Export->Stream...
SCH: Design->Create cellview->From cellview->
From: schematic To: functional (using the Verilog Editor)
o In the Cadence Abstract Generator, read in the GDSII & Verilog pin list
and set your technology switches, either manually, or mostly automatically
simply by reading in your process technology LEF (again, typically
supplied by your library vendor). Then, export LEF using ...
o ABS: File->Export->LEF
( )Technology
(o)Geometry
( )Antenna
Hope this helps, if not, call Cadence Customer Support 1-877-237-4911
or email them at 's-u-p-p-o-r-t-at-c-a-d-e-n-c-e-d-o-t-c-o-m' (remove
dashes, etc.).
They can walk you through the entire process as needed.
me
(tired of spam; you'll know me if you're a regular)
Srivathsan Krishnam
Try the Virginia Tech web-site:
http://www.ee.vt.edu/~ha/cell_library/distribution.html.
They provide LEF and .db for tsmc 0.25 micron tech.
Vathsan.
