Cadence Virtuoso automatic routing wire width consideration

[mohammad torabi]

Hi,
I have a LNA circuit. I need to use Layout GXL automatic router in Cadence to route the nets while the interconnect width has been considered. I mean I want to give width of net 1 as 200nm, the second one 400nm and so on.

Is there any way to do such automatic routing width consideration in Cadence?

Thanks

[Jean-Marc Bourguet]

mohammad torabi <tm.t...@gmail.com> writes:

> I have a LNA circuit. I need to use Layout GXL automatic router in Cadence
> to route the nets while the interconnect width has been considered. I mean
> I want to give width of net 1 as 200nm, the second one 400nm and so on.

I'd suggest to give min width constraints to the nets.

Yours,

--
Jean-Marc

[chaitha...@gmail.com]

Generating the layout:

After the schematic of the concerned Circuit has been completed and saved, the layout of the circuit can be done in two ways.
1. Manually placing the components in the and routing manually/assisted.
2. Using the custom digital placer for digital circuits/custom analog for the analog circuits. ( The circuit can be automatically routed)

Each of the above methods will be briefed in the following sections. (Only the custom digital placer is used as the circuit is DC-DC to controller.)

NOTE: From now on all the references made will be related to the cadence virtuoso IC 6.15


1.Manual layout Generation:

• Firstly, a new cell view should be created with layout as the type and it should be present in the same cell as the schematic is present. Once this is done the virtuoso layout L is opened by default.
• In the layout editor the corresponding transistors, resistors and capacitors are to be added from the same library as the corresponding instances present in the schematic.
• Once all the instances are present, some of the transistors that are to be used may not have a body contact. This should be given accordingly.
• Once all the instances are ready, the user can place them as he wishes in the layout editor.
• Once the instances are placed they have to be joined in sync with the connections present in the schematic. This can done by using the suitable metal layers for the inter connections.
• Once all the connections have been completed, the ports have to be added. These ports are specific with the metal layers in different libraries. e.g. <<Metal 1 pin>> is used for the port in tsmc180 with the port being in metal 1. The label follows the same in tsmc180.
• After the ports have bben given accordingly, the layout of the circuit can be tested using DRC and LVS.


This briefly completes how the layout is generated manually.

To use the assisted routing, once the instances are placed, go to launch->layout GXL.
Once the Layout GXL opens, there are few new icons beside the create via icon in the create tool bar. Here these various are used for assisted routing, point to point routing. Using these options the routing of the circuit is simplified to great extent.

Once the circuit is completed it is a practice to draw a pr boundary layer over the layout generated. This pr boundary layer is very crucial for smaller cells which are used as instances in larger circuits. The pr boundary determines how the cell gets placed when the auto placer is run.(The operation os the auto placer is covered in the next section). Once the cell is completed it is in practice to allign one vertex of the overall layout to the origin. This is done by
Edit->Advanced->Move origin.. then select the required point to be set as origin.

This essentially covers how the layout of the circuit can be done manually and routed using the layout GXL options.


2. Automatic Placement and Route (digital only):
The automatic placement options can be used to ease the design of large digital circuits like the DC-Dc converter discussed above.

Primarily to use the automatic placement generator and custom digital placer, we require the standard cell library of the technology that is being used.

But if the standard cell library is not available, then the lowest level cells that are used in the schematic created have to be made manually keeping few things in mind. If the cells are created in this way then there will not be any problems.

NOTE: The main reason to follow these rules is to take care that there will not be any DRC errors when the cells created are abutted by the placer.

Steps to follow while creating cells:
• The first and foremost thing to be implemented is to set the cells in such a way that all the cells which will be created SHOULD have the same height.(pr boundary to pr boundary as quoted in the previous section) This is very important as this greatly puts the placer within limits interms of the height of the rails that will be generated for the cells to be placed.
• Once the height of the cells has been fixed, the next thing is to create the cell such that this cell when abutted with a same cell or a different cell(same height) with any of its edge(viz top,bottom,left and right) it should not give any DRC error.
This crucial because even though a cell is DRC and LVS clean, when abutted with a similar cell might give rise various errors.eg min dist between M1, min CONT size,min dist between NWEL and so on.
This can be overcome only if the cells are created properly. One more important element is that the placer places the instances by using the pr boundary present on the instance(if pr boundary is absent, the bounding box is considered).

If the above steps are followed and the cells' layout is generated, there will be very few problems on the higher domain to deal with.



Assuming the cells are available to us(either STD cell ot the created ones)

Using the Custom Digital tool:

This consists of two parts:
1.Placement Planning
2.Custom Placer

The layout for the schematic and all the instances can be got directly using the layout GXL.
• Once the schematic has been finalised and saved, goto Launch->layout GXL.
• Now the layout connected to the schematic has been created. In the layout GXL, the instances corresponding to the schematic are generated by using
Connectivity->Generate->All from source.
Here in the window that pops up, the following should be checked (these are general settings, once understood they can be changed according to will)
In Generate:
Instances,I/O pins,PR boundary,Extract connectivity after generation.
In IO pins:
<choose the appropriate layer and label according to the tech file being used>.
• Creat lable – text display
• Click options – same as pin 2 times -ok
In PR boundary:, leave the settings un changed.
In Floorplan:
All
And press ok. This will generate all theinstances to be used and the pr boundary


Once the instances to be used and the boundary is generated we can use the custom digital.

NOTE: The generate all from source command will generate only the transistor (if it is present in schematic) but not the body of that transistor. However if the transistor is part of a smaller circuit where the layout of that transistor has the body, it will call that layout.

If the cells being used are created by the user and not from a standard cell, the cells generated have to be defined as standard cells or else the custom digital will not work. This can be done as follows:
Edit->component types
This opens a window and under the type “no component type” the cells created are listed.
To set as standard cell, right click on the cell, select “Add component type”, type in the desired name and click ok. After that right click on the cell, select “move cells” to the created component type. Once the cell has moved, select the component, In the attributes set the component class to “STDCELL”. Once the same is done for all the components, save and close.

Placement Planning:
• Go to Place->custom digital->placement planning.
• Select style “Assisted standard cell”
• In regions select the following
Allow for pins, Allow rows beyond region, Allow rows beyond cluster.
• In rows select the following
Utilisation inside rows, 100%.
% Area covered by rows. Spacing, 0.(this gives the spacing between the sets of rails ( set is the power and ground rails) generated).
• In rails, the power and ground rails are to be assigned with the required metal, thickness and net.
Pattern is to be selected by user.
The rail to rail spacing is the distance between power and ground rails.
Check create must join connection.
• In the layout generation check
regenerate all, preserve constrained objects, adjust boundary.
• Finally select ok.


These are the general settings to get 100% utilisation and very less wastage of space. (Once the settings are understood they can be changed by the user)

The placement planner generates the rails. These rails are the common power and ground rails. The instances present in the layout can be placed in between these rails.

The instances are automatically placed in their repective places using the digital placer.


Digital Placer:
• Once the placement planner has been run, the instances can be placed by using
Place->Custom digital->Placer
• In the placer the default settings present will place the instances properly in the best possible way. Filler cells cam be used to fill empty spaces.(The path of the filler cell has to be defined)
• Only the selected can be placed by checking the place selected only box.


This is the Placer which shall place the instances in between the rails.



Now to place the pins, the pr boundary that has been generated is resized to the required shape. Then place->pin placement.
The required pin is selected and placed at the required edge.(Press APPLY after each change)

Once the instances and the pins are placed the circuit has to be routed. This can be done by
Route->automatic routing.
In the window that pops up, the bottom and the top layer of the routing are selected according to the circuit that has to be routed.To allow the router to route the power and ground rails, select Options in the Net options and the locking of the power and ground is removed.
This option routes the circuit.




This completes the automatic layout generation using custom digital and automatic routing.