Partial Reconfiguration Problems
David Kramer
I'm currently working on a partial reconfiguration project, but I've got
some problems during the active and assembly phase.
I'm working with ISE 6.3i without any service pack and with ML310. I
also tried other ISE version (e.g. different service packs for ISE 6.3i
or ISE 7.1.04i), but got the same or other error messages. Other people
working in this field also told me to stay with ISE 6.3i.
The first problem occurs in the active implementation phase. When I try
to generate the partial bitstream bitgen produces the following error
message:
Running DRC.
WARNING:DesignRules:367 - Netcheck: Loadless. Net busmacro2/TNET(3) has
no load.
WARNING:DesignRules:577 - Netcheck: The signal GLOBAL_LOGIC1 was
unexpectedly
found to be routed outsite the route area for a Module in partial
reconfiguration mode.
WARNING:DesignRules:577 - Netcheck: The signal GLOBAL_LOGIC1 was
unexpectedly
found to be routed outsite the route area for a Module in partial
reconfiguration mode.
ERROR:DesignRules:10 - Netcheck: The signal "FFake_Gnd" is completely
unrouted.
ERROR:DesignRules:10 - Netcheck: The signal "FFake_Vcc" is completely
unrouted.
ERROR:DesignRules:580 - Blockcheck: The component PWR_VCC_0 was found to be
placed outside of the area infered by a range constraint. It is
likely that a
COMPGRP preference for a Module was modified prior to place instead of
modfifying the range constraint prior to map.
WARNING:Bitgen:25 - DRC detected 3 errors and 3 warnings.
Obviously some signals were not completely routed, but I've got no
warning and no error during PAR.
These signals are used to connect LUTs with the busmacros. The LUTs
create constant '0' and constant '1' signals.
So can someone explain why this error happens and how I can solve this
problem?
I read in a thesis that I should disable DRC (option "-d") in this phase
to get the bitstreams. If I do so, I get the following error message in
the assembly phase (also during PAR):
FATAL_ERROR:Guide:basgitaskphyspr.c:372:1.28.20.3:286 - A previous
module has
placed the comp: user_add/PWR_VCC_0 on the same site: SLICE_X43Y159
where the
current guide comp PWR_VCC_155 also needs to be placed. There exists at
least two guide files that contain logic 0/1 signals being driven
from the
site location. Process will terminate. To resolve this error, please
consult the Answers Database and other online resources at
http://support.xilinx.com. If you need further assistance, please open a
Webcase by clicking on the "WebCase" link at http://support.xilinx.com
OK, what can I do to avoid that these components are placed on the same
site?
Thanks in advance,
David
Andreas Kühn
To me this sounds as some lines of a bus-macro are not used and you want the to
keep the routing tool quite. Furthermore, I presume you try to assign some
static values to these lines.
So far not bad. These constants need to be declared inside an instance. In case
of reconfigurable instances these static signals are to be declared inside
these instances and provided to the bus-macro via the port list.
On the receiving side a drain in form of a signal is needed even if it isn't
connected to something processing.
By this all dummy signals are declared inside instances. Giving placement
constraints to tiny little things is somewhat time wasting and confuse the routing.
Finaly, your design should be build hierarchicaly from larger entities.
Cheers
akuehn