"ERROR:Simulator - Failed to link the design. Check to see if any previous simulation executables are still running."
jleslie48
Running Fuse ...
fuse -intstyle ise -incremental -o jb02_tb_isim_beh.exe -prj
jb02_tb_beh.prj -top jb02_tb
Running : C:\Xilinx\10.1\ISE\bin\nt\unwrapped\fuse.exe -ise C:/jon/
fpga_uarted_01/2009_01_28_jl_mod/11jlmod/uart_jb_02_goto/
uart_jb_02_goto.ise -intstyle ise -incremental -o jb02_tb_isim_beh.exe
-prj jb02_tb_beh.prj -top jb02_tb
Determining compilation order of HDL files
Analyzing VHDL file source/jb02_version_goto/New_UART_With_FIFOs/
kcuart_tx.vhd
Restoring VHDL parse-tree ieee.std_logic_1164 from c:/xilinx/10.1/ise/
vhdl/hdp/nt/ieee/std_logic_1164.vdb
Restoring VHDL parse-tree std.standard from c:/xilinx/10.1/ise/vhdl/
hdp/nt/std/standard.vdb
Restoring VHDL parse-tree ieee.std_logic_arith from c:/xilinx/10.1/ise/
vhdl/hdp/nt/ieee/std_logic_arith.vdb
Restoring VHDL parse-tree ieee.std_logic_unsigned from c:/xilinx/10.1/
ise/vhdl/hdp/nt/ieee/std_logic_unsigned.vdb
Restoring VHDL parse-tree unisim.vcomponents from c:/xilinx/10.1/ise/
vhdl/hdp/nt/unisim/unisim.vdbl
Analyzing VHDL file source/jb02_version_goto/New_UART_With_FIFOs/
kcuart_rx.vhd
Analyzing VHDL file source/jb02_version_goto/New_UART_With_FIFOs/
bbfifo_16x8.vhd
Analyzing VHDL file source/jb02_version_goto/New_UART_With_FIFOs/
uart_tx.vhd
Analyzing VHDL file source/jb02_version_goto/New_UART_With_FIFOs/
uart_rx.vhd
Analyzing VHDL file source/jb02_version_goto/data_gen.vhd
Restoring VHDL parse-tree ieee.numeric_std from c:/xilinx/10.1/ise/
vhdl/hdp/nt/ieee/numeric_std.vdb
Analyzing VHDL file source/jb02_version_goto/JB_Loki_Top.vhd
Analyzing VHDL file source/jb02_version_goto/jb02_tb.vhd
Saving VHDL parse-tree work.kcuart_tx into c:/jon/
fpga_uarted_01/2009_01_28_jl_mod/11jlmod/uart_jb_02_goto/isim/work/
kcuart_tx.vdb
Saving VHDL parse-tree work.kcuart_rx into c:/jon/
fpga_uarted_01/2009_01_28_jl_mod/11jlmod/uart_jb_02_goto/isim/work/
kcuart_rx.vdb
Saving VHDL parse-tree work.bbfifo_16x8 into c:/jon/
fpga_uarted_01/2009_01_28_jl_mod/11jlmod/uart_jb_02_goto/isim/work/
bbfifo_16x8.vdb
Saving VHDL parse-tree work.uart_tx into c:/jon/
fpga_uarted_01/2009_01_28_jl_mod/11jlmod/uart_jb_02_goto/isim/work/
uart_tx.vdb
Saving VHDL parse-tree work.uart_rx into c:/jon/
fpga_uarted_01/2009_01_28_jl_mod/11jlmod/uart_jb_02_goto/isim/work/
uart_rx.vdb
Saving VHDL parse-tree work.data_gen_pkg into c:/jon/
fpga_uarted_01/2009_01_28_jl_mod/11jlmod/uart_jb_02_goto/isim/work/
data_gen_pkg.vdb
Saving VHDL parse-tree work.data_gen into c:/jon/
fpga_uarted_01/2009_01_28_jl_mod/11jlmod/uart_jb_02_goto/isim/work/
data_gen.vdb
Saving VHDL parse-tree work.lprj_top into c:/jon/
fpga_uarted_01/2009_01_28_jl_mod/11jlmod/uart_jb_02_goto/isim/work/
lprj_top.vdb
Saving VHDL parse-tree work.jb02_tb into c:/jon/
fpga_uarted_01/2009_01_28_jl_mod/11jlmod/uart_jb_02_goto/isim/work/
jb02_tb.vdb
Starting static elaboration
Restoring VHDL parse-tree unisim.lut4 from c:/xilinx/10.1/ise/vhdl/hdp/
nt/unisim/unisim.vdbl
Restoring VHDL parse-tree std.textio from c:/xilinx/10.1/ise/vhdl/hdp/
nt/std/textio.vdb
Restoring VHDL parse-tree ieee.vital_timing from c:/xilinx/10.1/ise/
vhdl/hdp/nt/ieee/vital_timing.vdb
Restoring VHDL parse-tree ieee.vital_primitives from c:/xilinx/10.1/
ise/vhdl/hdp/nt/ieee/vital_primitives.vdb
Restoring VHDL parse-tree unisim.vpkg from c:/xilinx/10.1/ise/vhdl/hdp/
nt/unisim/unisim.vdbl
Restoring VHDL parse-tree unisim.muxf5 from c:/xilinx/10.1/ise/vhdl/
hdp/nt/unisim/unisim.vdbl
Restoring VHDL parse-tree unisim.muxf6 from c:/xilinx/10.1/ise/vhdl/
hdp/nt/unisim/unisim.vdbl
Restoring VHDL parse-tree unisim.fdrs from c:/xilinx/10.1/ise/vhdl/hdp/
nt/unisim/unisim.vdbl
Restoring VHDL parse-tree unisim.fdre from c:/xilinx/10.1/ise/vhdl/hdp/
nt/unisim/unisim.vdbl
Restoring VHDL parse-tree unisim.lut2 from c:/xilinx/10.1/ise/vhdl/hdp/
nt/unisim/unisim.vdbl
Restoring VHDL parse-tree unisim.mult_and from c:/xilinx/10.1/ise/vhdl/
hdp/nt/unisim/unisim.vdbl
Restoring VHDL parse-tree unisim.muxcy from c:/xilinx/10.1/ise/vhdl/
hdp/nt/unisim/unisim.vdbl
Restoring VHDL parse-tree unisim.xorcy from c:/xilinx/10.1/ise/vhdl/
hdp/nt/unisim/unisim.vdbl
Restoring VHDL parse-tree unisim.lut3 from c:/xilinx/10.1/ise/vhdl/hdp/
nt/unisim/unisim.vdbl
Restoring VHDL parse-tree unisim.fde from c:/xilinx/10.1/ise/vhdl/hdp/
nt/unisim/unisim.vdbl
Restoring VHDL parse-tree unisim.srl16e from c:/xilinx/10.1/ise/vhdl/
hdp/nt/unisim/unisim.vdbl
Restoring VHDL parse-tree unisim.fd from c:/xilinx/10.1/ise/vhdl/hdp/
nt/unisim/unisim.vdbl
Restoring VHDL parse-tree unisim.fdr from c:/xilinx/10.1/ise/vhdl/hdp/
nt/unisim/unisim.vdbl
Completed static elaboration
Fuse Memory Usage: 63060 Kb
Fuse CPU Usage: 1327 ms
Using precompiled package standard from library std
Using precompiled package std_logic_1164 from library ieee
Using precompiled package std_logic_arith from library ieee
Using precompiled package std_logic_unsigned from library ieee
Using precompiled package numeric_std from library ieee
Using precompiled package textio from library std
Using precompiled package vital_timing from library ieee
Using precompiled package vital_primitives from library ieee
Compiling package data_gen_pkg
Compiling package vcomponents
Compiling package vpkg
Compiling architecture lut4_v of entity lut4 [\LUT4("1110010011111111")
\]
Compiling architecture lut4_v of entity lut4 [\LUT4("0000000110010000")
\]
Compiling architecture lut4_v of entity lut4 [\LUT4("0001010101000000")
\]
Compiling architecture lut4_v of entity lut4 [\LUT4("0000000110000000")
\]
Compiling architecture lut4_v of entity lut4 [\LUT4("0110011000000110")
\]
Compiling architecture lut4_v of entity lut4 [\LUT4("0000000000000001")
\]
Compiling architecture lut4_v of entity lut4 [\LUT4("1000000000000000")
\]
Compiling architecture lut4_v of entity lut4 [\LUT4("1011111110100000")
\]
Compiling architecture lut4_v of entity lut4 [\LUT4("0000000001000000")
\]
Compiling architecture muxf5_v of entity muxf5 [muxf5_default]
Compiling architecture muxf6_v of entity muxf6 [muxf6_default]
Compiling architecture fdrs_v of entity fdrs [\FDRS('0')\]
Compiling architecture fdre_v of entity fdre [\FDRE('0')\]
Compiling architecture lut2_v of entity lut2 [\LUT2("1000")\]
Compiling architecture mult_and_v of entity mult_and
[mult_and_default]
Compiling architecture muxcy_v of entity muxcy [muxcy_default]
Compiling architecture xorcy_v of entity xorcy [xorcy_default]
Compiling architecture lut3_v of entity lut3 [\LUT3("00010000")\]
Compiling architecture lut3_v of entity lut3 [\LUT3("10010100")\]
Compiling architecture lut3_v of entity lut3 [\LUT3("11000100")\]
Compiling architecture lut3_v of entity lut3 [\LUT3("01010100")\]
Compiling architecture fde_v of entity fde [\FDE('0')\]
Compiling architecture srl16e_v of entity srl16e [\SRL16E
("0000000000000000")\]
Compiling architecture fd_v of entity fd [\FD('0')\]
Compiling architecture low_level_definition of entity kcuart_tx
[kcuart_tx_default]
Compiling architecture fdr_v of entity fdr [\FDR('0')\]
Compiling architecture low_level_definition of entity bbfifo_16x8
[bbfifo_16x8_default]
Compiling architecture macro_level_definition of entity uart_tx
[uart_tx_default]
Compiling architecture low_level_definition of entity kcuart_rx
[kcuart_rx_default]
Compiling architecture macro_level_definition of entity uart_rx
[uart_rx_default]
Compiling architecture rtl of entity data_gen [\data_gen(9,
(84,200,77,32,32,32,...]
Compiling architecture behavorial of entity lprj_top
[lprj_top_default]
Compiling architecture behavior of entity jb02_tb
ERROR:Simulator - Failed to link the design. Check to see if any
previous simulation executables are still running.
I added this code:
------------------------------------------------------------------------
-- A LABEL is a marker, a noop, but used for the GOTOL
constant op_LABEL : t_ubyte := 176; --NON standard ascii char.
subtype t_lbl_r is integer range 0 to 15; -- 16 labels are
availabe for now.
subtype t_lbl is t_ubyte_array(t_lbl_r);
function find_label(pgm: t_ubyte_array) return t_lbl is
constant p: t_ubyte_array (0 to pgm'length-1) := pgm;
variable it: t_lbl;
begin
it := (others => 0);
for i in 0 to (p'length-2) loop
if (p(i)= op_label) then
it(p(i)) := i;
end if;
end loop;
return it;
end;
constant the_label: t_lbl := find_label(the_program);
------------------------------------------------------------------------------------
to working and simulating code that had t_ubyte_array
already working:
------------------------------------
subtype t_ubyte is integer range 0 to 255;
--
-- and an array of those things.
type t_ubyte_array is array(natural range <>) of t_ubyte;
-- Function to convert the generic value into ROM-contents format
function contents(pgm: t_ubyte_array) return t_rom is
constant p: t_ubyte_array (0 to pgm'length-1) := pgm;
variable it: t_rom;
begin
it := (others => 0);
for i in p'range loop
it(i) := p(i);
end loop;
return it;
end;
-----------------------------------
Any ideas?
jleslie48
Ok, I think I got it.
Prior, I tried to simulate something with a syntax error,
I checked with the Windows Task Manager, and the *isim_beh.exe,
(in my example, jb02_tbg_isim_beh.exe) was still in the processes
section. I right-clicked on it, ended the process tree, and was then
able to restart simulation without error.