Hi,
I could not solve the problem of error with Queue. Could you help me?
I tried to use "Queue" in the following source code. However I got an error message:
[error] ChiselUtil.scala:359: Chisel.Queue was not properly wrapped into a module() call. in class Chisel.Queue
[error] (run-main-0) java.lang.IllegalStateException: 4mCODE HAS 4m1m10m4m 4m31mERRORS0m4m and 4m1m00m4m 4m33mWARNINGS0m
java.lang.IllegalStateException: CODE HAS 1 ERRORS and 0 WARNINGS
at Chisel.ChiselError$.checkpoint(ChiselError.scala:128)
at Chisel.Backend.elaborate(Backend.scala:791)
at Chisel.VerilogBackend.elaborate(Verilog.scala:1086)
I couldn't find any solution so far. I am happy if I could get any hint.
Many thanks,
--
Kentaro
Extracted source code: mRemoteMM.scala
================================================================
package Qsys
package mRemoteMM
import Chisel._
import scala.collection.mutable.HashMap
class mRemoteMM_IO(...) extends Bundle {
...
}
class mRemoteMM extends Module {
val pW_AVMM_DATA = ...
...
val io = new mRemoteMM_IO(pW_AVMM_DATA, pW_GLBL_ADDR, pW_LOCL_ADDR,
pW_CSRG_ADDR, pW_CSRG_DATA, pW_AVST_DATA)
//------------------------------------------------------------------------
// Queue test
// WHEN THIS PART IS REMOVED, COMPILATION IS PASSED W/O ERRORS.
val uFifo = new Queue(UInt(), 256) // entries = 256 (THIS MAKES THE ERROR)
uFifo.io.enq.ready := io.st_in.ready
uFifo.io.enq.valid := io.st_in.valid
uFifo.io.enq.bits := io.st_in.data
uFifo.io.deq.ready := io.st_out.ready
uFifo.io.deq.valid := io.st_out.valid
uFifo.io.deq.bits := io.st_out.data
}
object mRemoteMM {
def main(args: Array[String]): Unit = {
val cutArgs = args.slice(1, args.length)
chiselMainTest(cutArgs, () => Module(new mRemoteMM())) {
c => new mRemoteMM_Tests(c) }
}
}
================================================================