impossible to have rvalue for bit extract?

[Alexander Samoilov]

Let us define

    val io = new Bundle {

...

        val cline_2evict    = UInt(OUTPUT, width = num_levels)

...

got for a statement:

    io.cline_2evict(msb, msb) := state(0)

where msb is some value, say 39

PLRU.scala:49: error: reassignment to Node at /*? in class cache.PseudoLRU*/ Chisel.Bool(OUTPUT, width=1, connect to 1 inputs: ([Chisel.Extract] in cache.PseudoLRU)) in class cache.PseudoLRU

[error] (run-main) java.lang.IllegalStateException: CODE HAS 1 ERRORS/WARNINGS

java.lang.IllegalStateException: CODE HAS 1 ERRORS/WARNINGS

        at Chisel.ChiselError$.checkpoint(ChiselError.scala:119)

however assignment to the whole io.cline_2evict is fine, say the statement

    io.cline_2evict := UInt(0)

there were no errors.

What is the best way for assigning to a certain group of bits of UInt?

Create a new view as Vec[Bool] ?

Could you please give a piece of advice for a terse way for doing assignment for a group of bits?

Thanks!

Alexander

[Jonathan Bachrach]

there is no way to assign to subset of Bits in Chisel at this time.

best way is to use Vec[Bool].

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[Alexander Samoilov]

Ok, thanks!

Will try with temporary Vec[Bool]