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Hi all,
I see the very good reason to start with randomized register values for simulation. However, at least Quartus does not define SYNTHESIS in a default project setting. It can be added [1], but might be an obstacle for possible language switchers.
Do Xilinx tools or ASIC tools define SYNTHESIS?
Maybe the other way round would be to use a symbol SIMULATION:
‘ifdef SIMULATION
…$random
That would compile for synthesis and simulation even when not defined. Maybe ModelSim even defines a variable?
Cheers,
Martin
[1] into the .qsf file (thanks to Wolfgang):
set_global_assignment -name VERILOG_MACRO "SYNTHESIS=<None>"
Andrew Waterman
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Feb 9, 2015, 3:39:05 PM2/9/15
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Synopsys DC, Synplify, and Xilinx ISE all set this macro, and I've
seen other projects rely on it. I guess it's not truly standard, but
Quartus seems like the odd one out here. Perhaps it does define some
other variable during synthesis, so we can emit like
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Can you verify that it suffices for this use case in Quartus? I
remember that sometimes it isn't as powerful as the `ifdef because the
synthesis tool might think the thing inside the block is a syntax
error, which the comments don't fix.