ifndef SYNTHESIS and $random

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Martin Schoeberl

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Feb 9, 2015, 8:16:23 AM2/9/15
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Hi all,

I see the very good reason to start with randomized register values for simulation. However, at least Quartus does not define SYNTHESIS in a default project setting. It can be added [1], but might be an obstacle for possible language switchers.

Do Xilinx tools or ASIC tools define SYNTHESIS?

Maybe the other way round would be to use a symbol SIMULATION:

‘ifdef SIMULATION
…$random

That would compile for synthesis and simulation even when not defined. Maybe ModelSim even defines a variable?

Cheers,
Martin

[1] into the .qsf file (thanks to Wolfgang):
set_global_assignment -name VERILOG_MACRO "SYNTHESIS=<None>"

Andrew Waterman

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Feb 9, 2015, 3:39:05 PM2/9/15
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Synopsys DC, Synplify, and Xilinx ISE all set this macro, and I've
seen other projects rely on it. I guess it's not truly standard, but
Quartus seems like the odd one out here. Perhaps it does define some
other variable during synthesis, so we can emit like

`ifndef SYNTHESIS
`ifndef WHATEVER_QUARTUS_CALLS_IT
...
`endif
`endif
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Martin Schoeberl

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Feb 9, 2015, 3:57:08 PM2/9/15
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Found something for Verilog and Altera Quartus (maybe supported by the others as well?).

http://quartushelp.altera.com/13.1/mergedProjects/hdl/vlog/vlog_file_dir_translate.htm

Cheers,
Martin
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Andrew Waterman

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Feb 9, 2015, 4:40:31 PM2/9/15
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Can you verify that it suffices for this use case in Quartus? I
remember that sometimes it isn't as powerful as the `ifdef because the
synthesis tool might think the thing inside the block is a syntax
error, which the comments don't fix.
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Martin Schoeberl

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Feb 9, 2015, 4:56:53 PM2/9/15
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Ok, will check it out tomorrow and post if this fixes the issue.

Cheers,
Martin
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Martin Schoeberl

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Feb 10, 2015, 4:09:21 AM2/10/15
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Hi Andrew,

yes, these synthesis primitives work with Quartus.

Emitting following code would be very appreciated by (new) users working with Altera FPGAs:

// synthesis translate_off
`ifndef SYNTHESIS
integer initvar;
initial begin
#0.002;
blk = {1{$random}};
r1 = {1{$random}};
end
`endif
// synthesis translate_on

Cheers,
Martin
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Andrew Waterman

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Feb 10, 2015, 5:56:27 AM2/10/15
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OK, I created a pull request that should address this.
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Martin Schoeberl

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Feb 11, 2015, 4:47:31 AM2/11/15
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Thanks, will enjoy this simplification with the next Chisel release.

Martin
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