make rocket compile error

[전성일]

Hi chisel users,

I tried to compile my own configuration class to make a w/o L1 D-cache design to program on FPGA zc706 series.

My configuration file name is myTinyFPGAZynqConfig.scala

and the file consists of

--------------------------------------

package zynq

import cde.{Parameters, Config, CDEMatchError{

import rocketchip._

import rocket._

import coreplex.BuildTiles

import uncore.devices.NTiles

import uncore.tilelink.TLId

import uncore.agents.NAcquireTransactors

import testchipip._

import chisel3._

class myTinyFPGAZynqConfig extends Config(new TinyConfig ++ new ZynqConfig)

--------------------------------------

When I compile like this : 

~/work/fpga-zynq/zc706 $ make rocket CONFIG=myTinyFPGAZynqConfig

the error comes out!!

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[error] (run-main-0) java.lang.reflect.InvocationTargetException

java.lang.reflect.InvocationTargetException

at sun.reflect.NativeConstructorAccessorImpl.newInstance0(Native Method)

at sun.reflect.NativeConstructorAccessorImpl.newInstance(NativeConstructorAccessorImpl.java:57)

at sun.reflect.DelegatingConstructorAccessorImpl.newInstance(DelegatingConstructorAccessorImpl.java:45)

------------------------------------------------------------------------------------------------------------------

When I compile ZynqConfig which is not my own configuration but default configuration

~/work/fpga-zynq/zc706 $ make rocket CONFIG=ZynqConfig

This is compiled successfully.

I think when I make configuration file, there would be some kind of rules to compile successfully.

How to solve this problem?

Thanks.

[John Burke]

Since this was asked and answered successfully in the RISC-V HW group, linking the thread from there in case anyone else gets stuck in the future with this:

In RISC-V HW Dev