how to declare intermediate register

[Vishu Vivek]

I have working a code in which i unable declare a intermediate register

val rg_1 = Reg(init=Bits(0,1))

val lv_1 = rg_1

lv_1  :=  rg_1

in the above code lv_1 is wire and rg_1 is a register, but in verilog code it is declaring lv_1 as register, so please tell me how to declare intermediate register

Regards 

vishu

[Christopher Celio]

Do you mean you want the intermediate register to continue to exist in the generated Verilog? You can try "debug(rg_1); debug(lv_1)" to force the signals to continue to exist.

Your code is a bit confusing to me though. Lines 2 and 3 are redundant.   You're calling "val lv_1 = reg_1"?  That is creating a node called "lv_1" that points to the node "rg_1".  The Chisel backend is  going to generate that node once, and apply the name "lv_1" to it because you told it that "lv_1" is now the name of the node Reg(init=Bits(0)).


You probably want this:

val rg_1 = Reg(init=Bits(0,1))
val lv_1 = Bits() // declares lv_1 to be a wire
lv_1 := rg_1 // lv_1 is still a wire, that is assigned the value from the rg_1 node, as ":=" is the Chisel assignment operator
debug(lv_1) // make sure the backend doesn't prune this variable name from the generated source

-Chris

[Vishu Vivek]

Thanks chris for your reply, And sorry for the previous post which was not clear.
I also tried the below, which you suggested

val rg_1 = Reg(init=Bits(0,1))
val lv_1 = Bits()

lv_1 := rg_1

it is giving me the following error

[info] Compiling 1 Scala source to /home/gopi/dd/target/scala-2.

10/classes...
[warn] there were 305 feature warning(s); re-run with -feature for details
[warn] one warning found
[info] Running And1
// COMPILING class And1(0)
started inference
finished inference (7)
start width checking
finished width checking
started flattenning
finished flattening (1703)
resolving nodes to the components
finished resolving
started transforms
finished transforms
class And1 1703
checking for combinational loops
C.scala:-1: error: FOUND COMBINATIONAL PATH! in class And1
C.scala:-1: error:   (0) on line 105 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (1) on line 286 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (2) on line 104 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (3) on line 104 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (4) on line 104 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (5) on line 105 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (6) on line 105 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (7) on line 286 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (8) on line -1 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (9) on line 105 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (10) on line 286 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (11) on line 104 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (12) on line 104 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (13) on line 104 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (14) on line 105 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (15) on line 105 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (16) on line 286 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (17) on line -1 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (18) on line -1 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (19) on line -1 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (20) on line 121 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (21) on line 286 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (22) on line 120 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (23) on line 120 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (24) on line 120 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (25) on line 121 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (26) on line 121 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (27) on line 286 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (28) on line -1 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (29) on line 121 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (30) on line 286 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (31) on line 120 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (32) on line 120 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (33) on line 120 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (34) on line 121 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (35) on line 121 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (36) on line 286 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (37) on line -1 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (38) on line -1 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (39) on line -1 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (40) on line -1 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (41) on line -1 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (42) on line -1 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (43) on line -1 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (44) on line -1 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (45) on line -1 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (46) on line -1 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (47) on line -1 in class And1 in file C.scala,  in class And1
C.scala:-1: error:   (48) on line 44 in class And1 in file C.scala, lv_carry in class And1
[error] (run-main) java.lang.IllegalStateException: CODE HAS 50 ERRORS/WARNINGS
java.lang.IllegalStateException: CODE HAS 50 ERRORS/WARNINGS
    at Chisel.ChiselError$.checkpoint(ChiselError.scala:119)
    at Chisel.Backend.elaborate(Backend.scala:570)
    at Chisel.VerilogBackend.elaborate(Verilog.scala:770)
    at Chisel.chiselMain$.apply(hcl.scala:197)
    at Chisel.chiselMainTest$.apply(hcl.scala:221)
    at And1$.main(C.scala:1051)
    at And1.main(C.scala)
    at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
    at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:57)
    at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
    at java.lang.reflect.Method.invoke(Method.java:606)
[trace] Stack trace suppressed: run last compile:run for the full output.
java.lang.RuntimeException: Nonzero exit code: 1
    at scala.sys.package$.error(package.scala:27)
[trace] Stack trace suppressed: run last compile:run for the full output.
[error] (compile:run) Nonzero exit code: 1
[error] Total time: 2 s, completed 23 Nov, 2013 5:29:08 PM


Can u also tell me the difference between the two below statement

val lv_1 = rg_1

lv_1  :=  rg_1

Regards
vishu

[Jonathan Bachrach]

this says that you have a combinational loop in your circuit, that is, a cycle in your circuit graph that does _not_ contain a single register.  the code you sent does _not_ have a combinational loop.  it must be elsewhere in your code.  it’s hard to say without looking at your code.   

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