On Friday 27 July 2012 16:12:27 Andrew Bradford wrote:
> The default setting for the TPS65217 STATUS REGISTER (register 0x0A)
> bit 7 is "0" which should put the TPS65217 into SLEEP mode when
> PWR_EN (same net as PMIC_POWER_EN from the AM335x) is pulled low.
>
> I pull the PMIC_POWER_EN pin low by causing an ALARM2 condition
> within the AM335x real time clock module. When I set the TPS65217
> STATUS REGISTER bit 7 to "1" and then pull PMIC_POWER_EN low, I can
> successfully enter OFF mode. Exiting OFF mode (ie: powering up) is
> accomplished by inserting either USB or AC power while maintaining
> input power to the TPS65217 (either by using the other one than I'm
> plugging, or via lithium battery on P6) or by pushing the power
> button (on P9). But unless I perform one of these actions, the
> TPS65217 stays OFF, rather successfully. But OFF mode disables LDO1
> meaning my real time clock forgets what time it is, thus, I want to
> use SLEEP mode.
>
> But, when I attempt to enter SLEEP mode, I'm able to enter it, but
> then the TPS65217 powers right back up. I'm seeing the
> PMIC_POWER_EN line from the AM335x going low because of the ALARM2,
> but then 60 ms later, it goes high again. I assume this is because
> the PMIC_POWER_EN I/O goes to high-z pulled-up state while in reset
> (the data sheet doesn't say what the state of pins are when the
> AM335x is off, just during and post-reset, so I assume powered off
> state is the same as reset state).
See attached scope shot (hope it comes through). Tests on an A3 bone:
Ch1 is PMIC_PWR_EN.
Ch2 is VRTC (VLDO1)
Ch3 is RTC_PORz (LDO_PGOOD with resistor divider)
60 ms after PMIC_PWR_EN goes low, RTC_PORz starts falling. This will
reset the RTC IP block within the AM335x. The reset state for the
PMIC_PWR_EN pin is high. Thus, as soon as RTC_PORz is detected not-
high, the RTC resets (even though VRTC stayed up!) and pulls PMIC_PWR_EN
high again, enabling all the voltage rails on the TPS65217.
This is why I can't stay in SLEEP. The TPS65217 is declaring that an
LDO has fallen out of regulation (LDO2 has, it got turned off!) and thus
RTC_PORz is deasserted.
According to the TPS65217 data sheet, page 19, says:
* If the user disables a rail (either manually or through sequencer), it
has no effect on the PGOOD or LDO_PGOOD pin.
I read this to say, that if the TPS65217 is instructed to disable a
rail, PGOOD and LDO_PGOOD won't change state even if the rail its
monitoring is out of regulation.
Also, on page 19:
* If the user disables all rails (either manually or through sequencer)
PGOOD and/or LDO_PGOOD will be pulled low.
I'm not disabling "all rails," just all but LDO1. So LDO_PGOOD should
stay high.
Then, on page 20:
In normal operation LDO_PGOOD is high in ACTIVE and SLEEP state and low
in RESET or OFF state.
Which I read to say, if I go into SLEEP state, LDO_PGOOD should stay
high. It's not doing that for more than 60 ms...
> There's no pull-down on the PMIC_POWER_EN line to counteract the weak
> pull-up that is internal to the AM335x (at least during reset, but
> probably during power off, too). Possibly having a pull-down here
> would cause the Bone to never power up under some circumstances, but
> I've not attempted to rework one this way, yet.
If there was a pull down on PMIC_POWER_EN, I believe the bone would
_NEVER_ power up. That's not really useful.
> In OFF mode, the TPS65217 won't wake except for power button or the
> rising edge of a power source. But in SLEEP mode, the TPS65217 will
> wake because of PWR_EN going high or any of the conditions to wake
> from OFF mode. Because of this, I'd like PMIC_POWER_EN to stay low
> unless being driven by the AM335x to be high.
>
> Is this possible? Or am I most likely doing something else wrong?
> Am I forgetting a register setting in the TPS65217?
From u-boot, I'm able to write to the TPS65217 register 0x16
ENABLE_REGISTER to disable LDO2. When I do this, PGOOD_LDO stays high,
as expected.
From u-boot, I'm able to write to the TPS65217 register 0x1E
SEQUENCER_REGISTER_6 DEQDWN bit to initiate a power down (without
needing PMIC_PWR_EN to go low) and then I see SLEEP state voltage
levels, as I see above... VRTC stays up, PMIC_PWR_EN stays high (the
AM335x didn't pull it), but PMIC_PORz (LDO_PGOOD) goes low indicating
that either LDO1 or LDO2 is out of regulation.
This implies that LDO2 isn't under sequencer control during power down
and that LDO2 is going over current (the power LED draws more than 1 mA)
or either LDO1 or LDO2 have had a problem (which they haven't).
BUT! If I first disable LDO2 (turns the power LED off), then initiate a
power down, LDO_PGOOD _STILL_FALLS_!!! Which it shouldn't!
Guess I'll be visiting the e2e phorums... And calling my local rep...
And, populating R143 and depopulating R141 and R18. Which should then
set RTC_PORz to be controlled by the U17 gates based on an RC delay and
VRTC being up (LDO1). If that works, I'll let everyone know (I know
you're all on the edges of your seats!) :)
-Andrew