Fwd: BeagleWire current issues

[Patryk Mężydło]

Week report, today in other version :)

Hi mentors,

I finished work on SPI. The driver is here:

https://github.com/pmezydlo/BeagleWire/blob/develop/drivers/spi-ice40.c

feel free If you want review it, It looks like pretty well.

PWM component with top layer mapping module are ready: https://github.com/pmezydlo/BeagleWire/blob/develop/components/pwm.v

https://github.com/pmezydlo/BeagleWire/blob/develop/examples/pwm/top.v

Each FPGA ip core like spi or pwm are consist component and top module which mapping component to memory. When We want add next component to the existing. We just have to add offset to the next component. It’s very simple so i don't plan nothing changing.

For example:

assign en1 = mem[0][0];
assign polarity1 = mem[0][1];
assign period1[15:0] = mem[1];
assign duty_cycle1[15:0] = mem[2];

assign en2 = mem[3][0];
assign polarity2 = mem[3][1];
assign period2[15:0] = mem[4];
assign duty_cycle2[15:0] = mem[5];

pwm pwm1 (
   .en(en1),
   .period(period1),
   .duty_cycle(duty_cycle1),
   .polarity(polarity1),
   .clk(clk),
   .out(pmod1[0]),
);

pwm pwm2 (
   .en(en2),
   .period(period2),
   .duty_cycle(duty_cycle2),
   .polarity(polarity2),
   .clk(clk),
   .out(pmod1[1]),
);

Now I’m working on PWM driver and dts. It don't look difficult.

About GPIO, I added overlay: https://github.com/pmezydlo/BeagleWire/blob/develop/DTS/BW-GPIO-ICE40Cape-00A0.dts

But I have a problem with probing gpio-mmio driver. Really I can’t find way How to do it. Can you help me? I’m not blocked because I’m working on PWM but I want resolve this problem.

In a few days I will start working on UART module.

Thanks

Patryk