John Levine <
jo...@iecc.com> writes:
> "IBM's 360 and early 370 systems" by Emerson W. Pugh, Lyle R. Johnson,
> and John H. Palmer is the classic reference. WU's library has a copy.
>
> The 360/85 was a souped up 360/65, using much faster core memory and
> the fast ASLT logic from the /91. It was microcoded like the
> successful /65, not hardwired like the /75 and /91. IBM's high end
> computers, STRETCH, the /91 and the /195 had been phenomenally
> complicated, and the /85 seemed to be a relatively low risk addition
> to plug a hole in the product line. The original plan was to use
> 250ns core memory, three times as fast as the /65 or /91 core, which
> was a big technical challenge. Then someone came up with the idea of
> a cache, which initially met with great scepticism. But extensive
> simulations showed it would work, and it worked really well, so well
> that the main memory was slowed to 1000ns, allowing larger memories
> with longer cables, but it didn't matter since nearly all references
> were satisified from the 80ns cache. For jobs that didn't do much
> floating point, the cache made the /85 nearly as fast as the much more
> complex /91.
>
> The 370/165 was largely a reimplemented /85. All of the larger 370s
> had caches, and it was a long time if ever before IBM reused the
> complex out of order design of the /91.
claim is that half per processor throughput improvement from z10 to z196
was introduction of these old features of out of order execution and
additional work responsible for z196 to ec12 per processor improvement.
z900, 16 processors, 2.5BIPS (156MIPS/proc), Dec2000
z990, 32 processors, 9BIPS, (281MIPS/proc), 2003
z9, 54 processors, 18BIPS (333MIPS/proc), July2005
z10, 64 processors, 30BIPS (469MIPS/proc), Feb2008
z196, 80 processors, 50BIPS (625MIPS/proc), Jul2010
EC12, 101 processors, 75BIPS (743MIPS/proc), Aug2012
in the early 70s, i had gotten dragged into project doing hyperthreading
on 370/195 (which never shipped, part of the issue was that they were
never going to be able to retrofit virtual memory to 195) ... they told
me that biggest change from 360/195 to 370/195 were the couple
additional new 370 instructions and hardware instruction retry. 195
pipeline had out-of-order instruction execution but not branch
prediction and speculative execution ... so conditional branches drained
the pipepline. Carefully constructed codes would hit 10mips ... but
most codes typically ran 5mips. hyperthreading was to emulate two
i-streams (two processor operation) using red/blue bit implementation
described here in this article about end of acs/360 (two emulated
processors running conditional branch code at 5mips keeping 10mip
execution hardware utilized)
http://people.cs.clemson.edu/~mark/acs_end.html
Above also mentions acs/360 was shutdown because executives were afraid
that it would advance the state-of-the-art too fast and they would loose
control of the market and some of the features then show up in es/9000
20yrs later.
In the wake of failure of future system project
http://www.garlic.com/~lynn/submain.html#futuresys
there was mad rush to get products back into 370 pipeline ... including
kicking off 303x & 3081 somewhat in parallel; 3033 started out being q&d
effort remapping 168 logic to warmed over 20% faster chips from FS
(and 3081 using other warmed over FS technology)
http://www.jfsowa.com/computer/memo125.htm
at that time I was involved in 16-way smp effort ... and we had gotten
some of the 3033 processor engineers to work on it in their spare time
(lot more interesting than what they were doing with 3033). Initially
POK high-end people that it was really great ... and then somebody told
the head of POK that it might be decades before POK's favorite son
operating system had 16-way SMP support.
3033
https://www-03.ibm.com/ibm/history/exhibits/3033/3033_room.html
3081
http://www-03.ibm.com/ibm/history/exhibits/mainframe/mainframe_PP3081.html
when 3033 was out the door, they start on 3090 (overlapped with the
3081 work) ... finally as new effort
https://www-03.ibm.com/ibm/history/exhibits/mainframe/mainframe_PP3090.html
followed by es/9000
http://www-03.ibm.com/ibm/history/exhibits/mainframe/mainframe_FS9000.html
followed by ESA/390
http://en.wikipedia.org/wiki/IBM_ESA/390
and then finally get to 16-way with z900 in Dec2000
old post discussing decision to make virtual memory standard
on all 370s:
http://www.garlic.com/~lynn/2011d.html#73 Multiple Virtual Memory
posts mentioning SMP (&/or compare-and-swap instruction)
http://www.garlic.com/~lynn/subtopic.html#smp
--
virtualization experience starting Jan1968, online at home since Mar1970