Verible-verilog-format

[Pratyush Jain]

Hi Verible Users

      I tried to use the formatter for formatting system verilog files and I am able to do so successfully. However what I see is that when I run the formatter on the input file the output comes on the console or I can pipe it to some other file by giving a new file name. Is there an option, such that it can format the existing file itself.

Example: 

verible-verilog-format riscv.sv

Can it update the riscv.sv file itself ?

Thanks

Pratyush

[Henner Zeller]

On Wed, 5 Jan 2022 at 21:23, Pratyush Jain <pj...@tenstorrent.com> wrote:

Hi Verible Users

      I tried to use the formatter for formatting system verilog files and I am able to do so successfully. However what I see is that when I run the formatter on the input file the output comes on the console or I can pipe it to some other file by giving a new file name. Is there an option, such that it can format the existing file itself.

If you want the output in a different file, you can use the redirect functionality of your shell

  verible-verilog-format riscv.sv > formatted-output.sv

With the --inplace flag, you can modify the file directly, your second question:

  verible-verilog-format --inplace riscv.sv

This will format the file and replace the original file with the formatted version.

There are a few options you can play with to adapt the output to your liking:

https://github.com/chipsalliance/verible/tree/master/verilog/tools/formatter#usage

Cheers,

  Henner.

Example: 

verible-verilog-format riscv.sv

Can it update the riscv.sv file itself ?

Thanks

Pratyush

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