Where to start for implementation of a width mismatch rule?

[Wes Piard]

I would like to look into implementing a rule that checks for a width mismatch between LHS and RHS values. There have been a couple of issues already submitted: 

https://github.com/chipsalliance/verible/issues/1114

https://github.com/chipsalliance/verible/issues/2231

I have browsed the codebase a little, but I figured it would probably be more efficient for anyone here to provide some guidance on where to look. Does the ability to evaluate the total bit width of lhs/rhs expressions and port connections exist already? If so, do any current rules utilize this functionality? 

I feel like detecting width mismatches should be one of the first lint rules created since it is one of the most controversial topics when discussing SV vs. VHDL, etc. I fear that because this type of rule doesn't exist, there may not be any mechanism in place yet in Verible to easily implement it. Hopefully I'm wrong!

[David Fang]

I've commented on the above issues just now.

Verible at the moment doesn't evaluate types or widths; it's not an actual compiler (yet).  

To add this capability, one would start with the information that's present in the symbol table, (declarations' types, and symbol bindings/uses).

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