Verifying instruction trace decoding with TLA+
29 views
Skip to first unread message
christin...@gmail.com
Apr 20, 2023, 12:25:23 PM4/20/23
to tlaplus
An idle thought, and may not be possible, but I was wondering if one could in theory verify an instruction trace decoder with TLA+?
If you have an input program to the test chip (let's call that Y), and then you generate a trace, and decode it, you'll get an output allegedly showing all the instructions actually executed (let's call that X).
How do you know that the instructions were correctly decoded? Is there some way in TLA+ to model Y, and then check that X is a valid implementation?
I guess one would have to assume that any discrepancy was introduced due to inaccurate decoding, not an issue with the chip though...
If you have an input program to the test chip (let's call that Y), and then you generate a trace, and decode it, you'll get an output allegedly showing all the instructions actually executed (let's call that X).
How do you know that the instructions were correctly decoded? Is there some way in TLA+ to model Y, and then check that X is a valid implementation?
I guess one would have to assume that any discrepancy was introduced due to inaccurate decoding, not an issue with the chip though...
Felipe Oliveira Carvalho
Apr 22, 2023, 9:27:45 AM4/22/23
to tla...@googlegroups.com
Can instruction trace be modeled as a state transition system?
--
You received this message because you are subscribed to the Google Groups "tlaplus" group.
To unsubscribe from this group and stop receiving emails from it, send an email to tlaplus+u...@googlegroups.com.
To view this discussion on the web visit https://groups.google.com/d/msgid/tlaplus/975af696-81da-404b-ba99-0ab6d351ac08n%40googlegroups.com.
christin...@gmail.com
Apr 24, 2023, 8:31:38 AM4/24/23
to tlaplus
I suppose it can?
Reply all
Reply to author
Forward
0 new messages