Urgent - ASIC Verification Engineer @ Mountain View, CA

[aqua...@gmail.com]

Title: *ASIC Verification Engineer – Block level verification*
Location: *Mountain View, CA *


Skills: *ASIC Verification ,* *UVM,* *VCS simulator* ,*System Verilog * ,
*Verdi*

Description: Develop block level test plan, UVM test bench components
such as agents(drivers/monitors), scoreboard, constrained random testcases
based on UVM sequences, assertions. Develop and close functional coverage,
code coverage. Ability to independently execute on test plan, run
simulations and debug.

Responsibilities:

- 7+ years of ASIC verification experience
- UVM/System Verilog
- VCS simulator, Verdi
- 2, 3 projects experience with UVM based testbench, coverage closure

*Desirable:*

- Previous experience with PCIe, Ethernet, HBM-DDR, Processor
verification, floating point computational unit highly desired
- C/C++ experience is desired
- Scripting skills(Perl, Python)
- Formal verification experience is a plus



--
*Thanks and Regards,*
*RAYAPUREDDY HARSHA DEEPAK*
*Aqua Information Systems Inc.*
*300 N Pottstown Pike, Suite # 130*
*Exton, PA 19341*
*Direct: 215-666-6868*
*Fax: 215-600-1617*
*GTalk: HARSHA DEEPAK*