Hello all,
I noticed that even though AER signal (from DVS) is a 5V level signal, no level shifter is used to input the signal in RaggedStone2 FPGA board. According to the user manual the upper threshold is 4.1V and no higher voltage signal should be driven into the FPGA.
Am I missing something? Maybe a level shifter is used and was not mentioned? I am interested in this because I try to implement a similar setup.
Thank you