New Z67-SD Controller

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Norberto Collado

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Nov 5, 2020, 6:11:32 PM11/5/20
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I'm planning to refresh the Z67-IDE+ Controller as some parts will be difficult to get and the Micro-Controller is getting very expensive. These days new microcontroller's are about $4.00 to support the Z67 requirements. It is going to be a smaller version as I will like to use the SD card instead, to move away from the CF cards. It just need two 40-pin IC's and the glue logic.

I will keep same format to leverage current Z67-IDE+ images.

Attached is my vision on this project for next year; hopefully!

Norby
New_Z67_board.pdf

Terry Smedley

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Nov 18, 2020, 8:29:35 PM11/18/20
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Norberto:

SD cards would be nice, and kicking the DS89C430 to something cheaper also sounds good.

I'm late to the party with the Z67-IDE+ controller for the H8.   Got one built a few days ago.  I've only tried HDOS with it so far.  Everything seems to work except front panel booting from PAM-37.   If I first boot HDOS to an H37 device, I can then boot HDOS from the Z67 image using "BOOT DKx:".  And subsequent soft reboots from the Z67 device ("BYE", then return to reboot) work fine.  But a front panel boot from the Z67-IDE+ (either with the quick "PRIMARY" boot key, or by the universal DEVICE/PORT/UNIT sequence) results in a hang (no interrupts, front panel blank, reset required to recover).  I have only occasionally seen the boot image selection menu, but when it did come up, the H8 would hang as soon as I selected an image to boot.  I followed the advice to avoid multiple occurrence partitioning.

I'm using the Trionyx Z80 CPU, and the Org-0 port on that card.   The Z67 controller is the WH8-37 card, configured for Z67 on 174, Z37 on 170.  The H17 controller has been removed from the system.  I used "PREP67 174" and "PART67 174", and those programs ran to completion without error.  HDOS 2.0 INIT and SYSGEN also ran to completion without error.  Mounting a partition as a data drive works fine, and booting a Z67 image through the "BOOT" command also results in a stable system.  

I'm chewing through the possibilities, but thought I would ask if you have encountered issues with H8 PAM-37 booting before.

Terry

Glenn Roberts

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Nov 18, 2020, 10:04:15 PM11/18/20
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Terry: when you boot using “universal” sequence can you tell if the Z67-IDE+ consistently reads the software boot code record (LED shows brief disk activity)?  If not then the problem might be with PAM 37?; if yes then we could look at the software boot code.  I disassembled and commented this a while back. Norberto has the listing on his site

 

http://koyado.com/Heathkit/HDOS_H67_Boot_Code_files/bootcf0b%20Listing.pdf

 

this is the first code loaded off the Z67 and it is what presents the boot image selection menu. 

 

Since you have gotten this to run at least occasionally we know that at least those times the Z67 read worked.

 

Don’t know if you can spot anything in this code that would be an issue.  Or could compare to the boot code in BOOT and/or the H37 boot to see what those do that this doesn’t?

 

Do we know that the PAM-37 is fully compatible with the board?  Trionyx apparently sold their own firmware (below).

 

I also saw that the Trionyx board implements “software control of all three Z80 interrupt modes” (which the Heath and DG boards do not do).  Could it be that the interrupt processing is somehow not being initialized properly (since you’re observing inconsistent failures)?

 

 

 

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Terry Smedley

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Nov 18, 2020, 10:59:10 PM11/18/20
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Great troubleshooting ideas, Glenn. Thanks.

Yes, I can see the H8 hit the drive as soon as the boot keys are pressed on the H8.  As far as the PAM-37 goes, Tryonix provided documentation on using it with their board, and I have not previously observed any incompatibilities.  Which is not to say that the intervening decades haven't revealed some incompatibilities that weren't initially observed.

The interrupt issue you mention is certainly a possibility, as interrupts are lost when the boot process hangs.

I will look at the boot code - thanks for the reference. 

Perhaps this is a good reason to put in Norberto's latest Z80 board :-)

Terry

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Glenn Roberts

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Nov 19, 2020, 8:54:50 AM11/19/20
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You could also try replacing the Heathkit boot process with the Quickstor one which uses a different boot code.  Ken Owen can probably help with any questions.  He has a lot of info on Norberto’s site though, including some images that you can burn directly to a CF card…

 

http://koyado.com/Heathkit/Z67-IDE-plus.html

 

there’s a lot of stuff there and not that well organized but Ken or Norberto can probably help you figure it out.

 

 

image001.png

terry.smedley

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Nov 19, 2020, 11:23:37 AM11/19/20
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Glenn

A CF adapter for my Windows computer is on its way so I will be able to try the Quickstor boot process using Ken's images.  I may not have a faithful enough emulator of H19 ANSI mode to navigate the QuickStor menus.

Terry

Kenneth L. Owen

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Nov 19, 2020, 12:04:47 PM11/19/20
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Hi Terry,

 

I have teamed with Norberto to try to give implementation support to the group members who are trying to implement the Z67-IDE and Z67-IDE+ on their Heaths.

 

I have increasingly been less active on the group over the past 10 years as my wife was not well, declining in health and needed me more that the group!  She passed away in August of this year and I am trying to get back into things that had to fall by the wayside over the past 10 years.

 

Feel free to contact me directly for your needs.  It may take me a bit to get back up to speed on things, but I will give you my best.  My email addy is: tx83...@bellsouth.net

 

  • ken

 

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Norberto Collado

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Nov 19, 2020, 12:06:40 PM11/19/20
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Please try the following image and use the Windows tool to deploy it on CF#0.

 

Image: http://koyado.com/Heathkit/Z67-IDE-plus_files/H37_H67_Heath_HDOS_CPM_Drive0.zip

Tool: http://koyado.com/Heathkit/Z67-IDE-plus_files/Z67-IDE%20Windows%20Imaging%20Utility.zip

 

If booting from this image fails, then you have a corrupted PAM-37 monitor or a marginal broken CPU.

 

Make sure all the switches on the H67 are set to the “ON” position (DS1), to the right of the arrow on the switch.

 

Thanks,

Norberto

Norberto Collado

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Nov 19, 2020, 12:11:22 PM11/19/20
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Also I developed the Z67-IDE+ on the Trionyx CPU using the PAM-37 monitor.

 

Norby

Steven Hirsch

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Nov 19, 2020, 1:43:15 PM11/19/20
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On 11/19/20 12:04 PM, Kenneth L. Owen wrote:

> I have increasingly been less active on the group over the past 10 years as
> my wife was not well, declining in health and needed me more that the
> group! She passed away in August of this year and I am trying to get back
> into things that had to fall by the wayside over the past 10 years.
Hi, Ken.

I'm so sorry to hear about your wife. My condolences and best wishes go out
to you!

Steve

Terry Smedley

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Nov 19, 2020, 2:35:01 PM11/19/20
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Ken:

Thank you for your reply and kind offer to help.

I am very sorry to hear about your wife.  

The fine work you have already done during development of the card will resolve my issues, I'm sure.  

Terry

Terry Smedley

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Nov 19, 2020, 2:40:57 PM11/19/20
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Norberto:

Thanks for confirming that there is not a fundamental compatibility problem with the Trionyx and PAM-37.  

I will have a CF writer today.  I will try the images you mentioned.

I will also have a look at the myriad of jumpers on the Trionyx card.  I have a stack of addenda describing PCB fixes and jumper settings that were changed early in the card's life as incompatibilities surfaced.  I'm looking closely at the addenda related to interrupt handling.

Terry

Glenn Roberts

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Nov 19, 2020, 8:27:48 PM11/19/20
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It seems like Trionyx did this a lot.  I had a few of their memory boards and there were multiple patches applied over time.  The temptation is to remove them but they were all bug fixes or enhancements, if you can track down the documentation…

 

Terry Smedley

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Nov 19, 2020, 8:40:00 PM11/19/20
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Norberto:

Is there a hex/bin/S19 image of the PAM-37 ROM on your web somewhere?  The link to the ROM images at the github site is broken.

I loaded the H37/H67 image you suggested, and got similar results.  I can see the read request for the SBC go to the H67, but the H8 hangs right away.  Pulled both the Trionyx and WH8-37 cards, confirmed all jumpers, reseated all ICs.  All the Trionyx jumpers/switches are set to their defaults as noted in their "Standard Jumper Selections" document.  I had also made the "Extended Performance Modification No. 01", which bypassed the LS244 at U51 as recommended by Trionyx.   I had also previously made the "Extended Performance Modification No. 02" to install the WH8-37 card, and "... No. 03" to install the PAM-37 ROM at U24.  Per those instructions from Trionyx, I have SW2 1-6 OFF, and 7-8 ON.

As before, I can warm boot to the H67 image ("BOOT DK0:"), with normal startup and a stable system.

If you can point me to the PAM-37 image, I will burn a new copy and give that a try.

Thanks.

Terry

Norberto Collado

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Nov 19, 2020, 9:26:07 PM11/19/20
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Is there any information coming out of the serial port on the Z67-IDE+? 

Norberto

Terry Smedley

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Nov 19, 2020, 9:39:36 PM11/19/20
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The serial port is quiet, after displaying the "ready to transfer" message.

Terry

Terry Smedley

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Nov 20, 2020, 2:31:30 AM11/20/20
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Norberto:

Thanks for the PAM-37 link.  I created a new ROM, but get the same results.  If I repeatedly reset the H8, and do a PRI H67 boot, I can see the SBC menu about 1 in 20 attempts.  Even when that boot menu displays, I have been successful at booting an image from there only once in the hundreds of times that I've tried - but that one time did result in a normal HDOS boot and stable system.  This just smells like a timing issue to me.

I think I will extract the PAM-37 "BH67" boot code and try to run it standalone, with plenty of progress prompts.  Hopefully, I'll be able to identify where it is hanging and figure out what is unique about that process compared to the warm boot code.

The PAM-37 files you linked say that an official listing for PAM-37 could not be found.  I see that's been a while ago, but I have Heath manual 595-2908, "Using the H-8 Computer with the PAM-37 Panel Monitor" that contains a complete assembly listing for PAM-37, on pages 33-147.  That's the listing I will use to duplicate the BH-67 code, because it's "Heath assembler friendly" and uses the standard XTEXT decks.

Terry

Terry Smedley

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Nov 20, 2020, 2:43:12 AM11/20/20
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Norberto

Is there a "magic hidden menu option" that would display the conversation at the H67-IDE+ end of the link?  

Terry

On Thursday, November 19, 2020 at 6:26:07 PM UTC-8 Norby wrote:

Norberto Collado

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Nov 20, 2020, 5:05:40 AM11/20/20
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If you leave the system hung for at least 5 minutes, do you get any other information? Just curious.

 

If not, send me the Z67-IDE+ to check it out.

 

Address: Norberto, Collado, P. O. Box 988 Hillsboro, OR 97123-0988

 

Thanks,

Norberto

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Norberto Collado

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Nov 20, 2020, 5:07:48 AM11/20/20
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Yes, type the “esc” command to enter the menu.

 

Norberto

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Norberto Collado

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Nov 21, 2020, 3:13:57 AM11/21/20
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Any updates???

Terry Smedley

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Nov 21, 2020, 3:59:15 AM11/21/20
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Norberto:

I was trying to give you a break from my issues for a day or two.  :-)  I have worked through a number of different scenarios and here is what I have found:

First, to answer your question about serial port data:  I do not see anything on the serial port after the controller boots and displays the "ready to copy" message.  My gut tells me that the Z67-IDE+ is not where the hang occurs.  I believe it has responded to the commands from the WH8-37 board and thinks that life is good.  Initiating a cold boot sequence results in a very consistent activity pattern.  The Z67 activity light flashes rapidly in succession about four times, a very brief pause, then one more single activity pulse.  With that last pulse, the H8 front panel blanks, interrupts are off.  No messages are posted on the Z67-IDE.    I believe that the first set of pulses is reading the MBR, and the last pulse is reading the SBC.'

Here's an interesting twist.  If I prep the drive with PREP67, then use the ZDS PART program, I will see the partition selection screen at boot every time.  But choosing a bootable partition from that screen results in the front panel out system hang.  But if I PREP67 followed by the customized PART67, I never see the selection screen - it's lights out as soon as that single activity pulse occurs.  I've done this experiment many times - it's very reproducible.

I read in the documentation that re-running PART67 to revise the partition layout didn't work.  I have observed that often - not always - if I attempt to re-run PART67, I'll get an error message that the superblock checksums are bad.  The partitions continue to mount and warm boot just fine.  Is this the normal behavior when re-running PART67?  I've seen that message at one time or another on all four of the Transcend 2GB CF cards I have.  But again, that's only on a re-run of PART67, and the partitions continue to operate normally.

I also read in the documentation that the Z67-IDE microcontroller serial port displayed a message that it had intercepted commands from PREP67.  I see no such message when running PREP67, but I was suspicious that perhaps that was true of some earlier version of the code but had been changed.  

I apologize for my inquiry about the menu.  I was aware of the ESC menu.  I meant to be clear in asking if there was a further debug option where I could view a trace of the commands and data going in and out to try to get a handle on where in the boot process the H8 was hanging.

I am using the Z67 controller section of the WH8-37 card.  From the postings I've read, it seems like that's not a very popular option.  Are there others that are using that card successfully with the Z67-IDE?  It sounds like most folks have used your H8-67 card either because they didn't have the WH8-37, or because they wanted to address the Z67 SASI controller at 27x.

Since the boot code for the QS partitions is at least slightly different, I was just starting to head down the path of trying to bring up a QuikStor setup to see if that behaves any differently.  Unfortunately, I don't think I can quickly use the QS images on your web site, because they have the Z67 controller at 170 or 270.  I'm trying to get an ANSI-capable emulator up and running now to start a QS system from scratch.  I may pull cards and temporarily put the H67 portion of the WH8-37 card at 170 so I can use one of the canned images.

Lastly, I will confirm that I have moved a lot of data across the Z67-IDE and have not had the slightest hiccup during reads and writes.  Cold booting is the issue I am struggling with.

Terry

Norberto Collado

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Nov 21, 2020, 4:18:35 AM11/21/20
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Thanks for the update! Please check your serial board to be configured  properly. Also check your RS-232 handshaking signals as well. It seems to be stuck polling the serial port based on your description, but not sure. Have you seen on the Z67-IDE+ any watchdog timeout messages?

 

When you use the PAM-37+ image I gave you, do you see on the screen “H8 Initialized…” on power-on?

 

I will review your data tomorrow again. I can send you a modify FW for the microcontroller that will display the command and data read/written.

 

Thanks,

Norberto

Any updates???

Error! Filename not specified.

Terry Smedley

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Nov 21, 2020, 4:33:28 AM11/21/20
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Norberto:

Yes, the modified PAM-8 displays the "H8" message on powerup/reset.  Thanks for the link to that.

The serial connection to the Z67-IDE seems to be OK.  I can ESC to the menu and see what appears to be a normal response to menu commands.  When the board is RESET, I see the status/signon screen that seems normal.  I am using the serial window in the MTK2 program.

I have never seen any watchdog messages, or any other messages, when the Z67-IDE is in operation.  Should there be some kind of message when running PREP, or when processing data normally?

Terry

Glenn Roberts

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Nov 21, 2020, 9:58:21 AM11/21/20
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You say when you use the ZDS PART/PREP you get the boot selection menu every time. Thats great. When you select from that menu it will load whatever boot code was installed during the INIT process (I'm assuming HDOS). Were you able to INIT the partition and SYSGEN successfully?  Assuming you boot from a floppy on your '37 you will need the correct Z67 device driver for DK: on your boot floppy or the INIT won't install the correct HDOS boot code. 

I am the one who modified PART67. The modifications let you use 15 meg instead of 10. Also lets you specify port number as I recall? (I'm not at my system now)

I use the WH-8-37 board to talk to the IDE+ and have seen no issues.  Works fine at all CPU speeds.

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Glenn Roberts

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Nov 21, 2020, 10:52:58 AM11/21/20
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My guess is the H67 driver you used to INIT had the wrong port. There should be versions for all 4 possible ports on Norberto's site. There are also instructions there from ken on how to patch it. Look under the Z67IDE page i think (not IDE+ one)

Terry Smedley

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Nov 21, 2020, 2:13:31 PM11/21/20
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Hi, Glenn

Thanks for the great suggestions, and especially for confirming that the WH8-37 card is working for you!

I have confirmed the H67 driver I am using is the one for port 174Q

And I observe that when a CF is loaded with Ken's image for H67/174 + H37/170, I get identical response there - no display of the selector screen, and no cold boot.  But I can mount it or warm boot into it (just as with the partitions that I created and formatted).

Since I can warm boot into Ken's H67 image, I created new H37 boot disks using only the software on Ken's disk.  After PREPing and PARTing from those "pure" copies of Ken's system, I still get the same result - unable to cold boot, but those partitions are mountable and can be warm booted to a stable system.

I'm attempting to create a QS HDOS system now to see how that different boot process might work.

And lastly, I'm gathering components to build a second Z67-IDE+ card.

Thanks again for your suggestions.

DId you get the information I sent you about the H8 I2C implementation?

Terry


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Glenn Roberts

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Nov 21, 2020, 3:39:14 PM11/21/20
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Hmm. Stumped for now.

I bet you get it working with the quikstor version ...

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Kenneth L. Owen

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Nov 21, 2020, 3:41:25 PM11/21/20
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Hi Terry,

 

I have been out of the loop for quite a while due to caring for my wife.  Since I don’t remember the image file below, I can’t give you very specific instruction, you might want to pull the Z67 card and set all switches on.  This will give you the SASIX boot menu if that image is using it.  Also, you can try the command line:        “Boot SS-0 <cr>                          If the image is using the SASIX Boot system it should boot partition 0 of the system.

 

  • ken

 

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Terry Smedley

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Nov 21, 2020, 4:18:54 PM11/21/20
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Yes, the QuikStor configuration works fine.  I haven't checked CP/M yet, but the HDOS version works fine.  The only emulator I could lay hands on quickly that would do "good enough" ANSI for SASIX was PUTTY.  It was a little kludgy getting through SASIX, but I eventually guessed the right command keys to use.

The only thing that doesn't work (which I anticipated) was the QS-Boot menu, which apparently requires an ANSI emulation good enough to report its baudrate.  A  minor issue that I will eventually work around with better emulation.

I can say that Dean Gibson's handiwork is readily apparent here - the speed of the QS disk access is palpably faster than with the ZDS drivers.

Thanks for all of your suggestions, including the idea that the QuikStor boot code might behave differently.  At some point, I would like to uncover the root cause of the Heath configuration incompatibilities, but that can wait for another day.

Terry



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Norberto Collado

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Nov 21, 2020, 5:53:40 PM11/21/20
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If HDOS QuikStor works fine, then you were using the wrong port #. Great news.

 

Norberto

Terry Smedley

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Nov 21, 2020, 6:39:50 PM11/21/20
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Well, I don't think that explains why the canned image for 170/174 didn't work either!

Terry


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Kenneth L. Owen

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Nov 21, 2020, 9:13:08 PM11/21/20
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Hi Terry,

 

The SASIX boot screen needs the H-19 Terminal using VT-52 mode and the Heath enhancements.  If you don’t have an H-19 Terminal, several on the group have H-19 emulators that they have developed.  I believe George Farris has one that will work with the SASIX boot system.  Contact him here in the group.

 

  • Ken

 

 

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Terry Smedley

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Nov 22, 2020, 9:17:26 AM11/22/20
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Thanks, Ken!

Terry

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Norberto Collado

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Nov 24, 2020, 4:06:20 AM11/24/20
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 Updates:
 
I decided to eliminate the 82C55 IC and to use some TTL IC's to do the same work. So the board is just the Micro-controller + logic to support two SD cards. I was able to complete the schematics and layout the module by leveraging the schematics from the original Z67-IDE controller.
 
The $5.00 Micro-controller supports the SPI bus and the I2C bus, so there is not need to do a bit bang to initialized the SD card or the I2C LCD board.
 
On the SD card specs, I lost previous knowledge (getting old), so I will appreciated a good pointer on how to initialized, read/write from the SD card. My plan is to load current Z67-IDE+ images and it should read/write them.
 
Still deciding to use SDCC C compiler to have a better interface. To do a quick test, I will use current code written in assembly code to get the best performance to test the HW. The only module to debug will be the SD code as everything else has been already tested. 
 
This new board should provide continuity to the previous Z67-IDE boards as some parts are expensive or hard to get for years to come.
 
Attached is a picture of the new Z67-SD board.
 
Thanks,
New_Z67_board.pdf
H8-Z67-SD CONTROLLER.JPG

Glenn Roberts

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Nov 24, 2020, 5:46:28 AM11/24/20
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Great work Norberto! Good to see more room around mounting holes as current design requires nylon hardware or fiber washers to prevent shorting.


Would it be possible to accommodate accessing SD card from the front? (When mounted in 3.5” drive position). With current design I must open the chassis to change out the CF card

Sent from my iPad

On Nov 24, 2020, at 4:06 AM, Norberto Collado <norberto...@koyado.com> wrote:


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Douglas Miller

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Nov 24, 2020, 7:20:33 AM11/24/20
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Had a thought, and keep in mind I know nothing about this microcontroller and it's SDK. But, does the SDCard library support a partition table (e.g. MS-DOS boot sector (MBR), or more modern forms) on the SDCard? And if so, do we want to use it? This would, in theory, allow one to partition the huge SDCard into "reasonably" sized partitions for HDOS or CP/M on the host, and no longer be constrained by the 128M fixed segment size. It makes it easier to update and backup images on the card from the host PC, and provides the potential for less wasted space. Still, it's a trade-off and I'm not sure if it is worth it.

And, of course, Glenn's comment about making sure one can insert/remove the cards without disassembling the unit would be essential.

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Norberto Collado

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Nov 24, 2020, 8:54:05 PM11/24/20
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Norberto Collado

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Nov 24, 2020, 9:15:27 PM11/24/20
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The 128MB limit is because of CP/M supporting 8MB * 15 partitions + spares MB. HDOS uses 15MB if using Glenn changes.  This allows me to divide a 4GB CF card into 128MB chunk sizes. What is a reasonably sized partition?

 

I know that the SCSI2IDE controller was tested with a Z80 using the SDCard MSDOS library and performance was very poor. With CF cards was much better.

https://www.retrobrewcomputers.org/doku.php?id=boards:other:scsi2ide:start

 

Thanks,

Norberto

 

 

From: "se...@googlegroups.com" <se...@googlegroups.com> on behalf of Douglas Miller <durga...@gmail.com>
Reply-To: "se...@googlegroups.com" <se...@googlegroups.com>
Date: Tuesday, November 24, 2020 at 4:20 AM
To: "se...@googlegroups.com" <se...@googlegroups.com>
Subject: Re: [sebhc] New Z67-SD Controller

 

Had a thought, and keep in mind I know nothing about this microcontroller and it's SDK. But, does the SDCard library support a partition table (e.g. MS-DOS boot sector (MBR), or more modern forms) on the SDCard? And if so, do we want to use it? This would, in theory, allow one to partition the huge SDCard into "reasonably" sized partitions for HDOS or CP/M on the host, and no longer be constrained by the 128M fixed segment size. It makes it easier to update and backup images on the card from the host PC, and provides the potential for less wasted space. Still, it's a trade-off and I'm not sure if it is worth it.

Norberto Collado

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Nov 24, 2020, 9:24:22 PM11/24/20
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Glenn,

 

I saw this board which shows that I need to extend the SD adapter out of the board to be access from the front. I will incorporate such change as we can do a 3D print case for it. See attached picture.

 

Norberto

SD CARD FRONT LOADING.png

Douglas Miller

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Nov 24, 2020, 9:44:04 PM11/24/20
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It may be better to just access the SDCard "raw", but I thought I'd ask. FYI, CP/M 3 does not have the 8M partition limitation, it can support a 256M drive (partition). It just seemed that getting out of the fixed-size segment might be worth exploring.

I'm not sure why the performance would be worse, seems to me that the partition table should be read only once at power-up of the Z67-IDE (or Z67-SDC as the case may be) - or rather at insertion of the SDCard if supporting hotplug, so I don't think the Z80 comes into it at all. Keep in mind, I'm suggesting that the microcontroller in the Z67-SDC use the MBR partition table, not the Z80 (CP/M). I was thinking that each MS-DOS partition on the SDCard be "exported" by the Z67-SDC as a raw disk, and CP/M / QuickStore / HDOS, whatever might sub-partition it as needed. So, instead of the fixed-size 128M "segments", the Z67-SDC just reads the MBR partition information and uses those partitions instead of the fixed segments. But, if the SDK you are using does not have library support for MBR, it wouldn't make sense. And if the microcontroller is limited in speed and/or memory, it also may not make sense.

Glenn Roberts

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Nov 24, 2020, 9:56:13 PM11/24/20
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That’s exactly what I was thinking. Thanks!

Norberto Collado

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Nov 24, 2020, 10:12:51 PM11/24/20
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The current Z67-IDE+ supports only the 128MB when using the switches to divide the CF card. If you leave the switches at “00”, then all 1GB range is available to the system. Today 256MB partitions are supported, but the user must avoid selecting such partition with the switches. So for 256MB, the user will select “00” and the next available partition will be “002” as “00”-> “01” will be used by CP/M3 OS. For this controller, I will use the 256MB range to divide the  SD card as it makes sense to redo some of the Heath CP/M-HDOS images.

 

Please send me a CP/M3 256MB image to test with the current Z67-IDE controller. I want to see it any issues.

 

I will review about the MBR to understand on how that works. Yes, we need to use raw as it is a 20MHz 8bit CPU with 1KB of RAM. It is faster than the original SASI 10MB hard drive.

 

Thanks for the feedback,

Douglas Miller

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Nov 24, 2020, 11:38:52 PM11/24/20
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I was not aware that the Z67-IDE+ did not enforce the end of the segment. So, it is possible to corrupt later segments on a CF card?

I mis-quoted earlier, CP/M 3 supports drives of up to 512M each.

The MMS "master boot record" supports 8 (or maybe 9) partitions, so for CP/M 3 one could use 4+G of space on the card. I'll need to make sure my Z67-IDE+ emulation supports the above behavior, and then I can create and test a CP/M 3 image that uses more space.

It is sounding like maybe this new controller is not going to work well with MBR, even *if* the SDK contains code for it. It would make handling the "segments" on the host PC easier/safer, but it may not be practical to implement on the microcontroller. It also would not have the behavior of the old Z67-IDE+ segments, as you cannot access beyond the end of an MBR partition like you can with the segments.

Glenn Roberts

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Nov 25, 2020, 7:41:58 AM11/25/20
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The Z67 uses the interface protocol defined in the MRX101D controller which was originally designed for Memorex 101 disk drives.  This is what Norberto has emulated in his implementation.  The interface specification is here

 

http://koyado.com/Heathkit/Z67-IDE_files/MRX101D.controller.pdf

 

It uses sectors that are 256 bytes in size.  the “Class 0” command (I/O) data structure (p. 14) allows 21 bits for sector addressing and three bits for logical unit number.  Norberto’s controller maps the logical unit number to the CF (or soon to be SD) card, so LUN 0 is card 0, LUN  1 is card 1, etc. (though this could presumably be changed via software to refer to portions of the same SD/CF card).  Each card can have 2**21 sectors which is 2,097,152 sectors or 538,870,912 bytes ( ½ Gig).  So without software changes to the IDE+ software you’re constrained to ½ G per SD/CF card.  the thumbwheel switches let you extend that space by remapping it within the card in 128 Mbyte chunks, but for any given thumbwheel setting your limited to the ½ Gig aligned to any given 128 Meg boundary specified by the switch settings.

 

If we were to partition the card into 8 logical units (rather than have the LUN refer to the physical card slot) you could support up to 4 G per card, however currently the LUN is used to select different cards. Not sure how hard it would be to redefine sector size (e.g. to 512, 1024, etc.) but that might be another option.

 

Frankly ½ Gig is so much space from an HDOS/CP/M concern I’m not sure it’s worth spending a lot of time on.

 

Now how much of the ½ Gig is usable at the OS level is a function of the drivers and BIOS definitions.  The Heath/Zenith HDOS drivers used a 2-byte sector addressing scheme (presumably more efficient than juggling 3-byte entities).  With 2 bytes you can address at most 65,536 sectors or 16 megabytes..  I believe the Quickstor and CP/M drivers are smarter and can access more.

 

Norberto implemented a special feature of his firmware that uses a control byte to access the full ½ Gig address space.  I use this in my “jukebox” software to access a whole swath of space that’s “invisible” to HDOS otherwise.

Douglas Miller

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Nov 25, 2020, 8:04:52 AM11/25/20
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right, I had neglected to consider the SASI protocol in computations of usable space. CP/M 3's 512M per drive capacity matches the SASI protocol max capacity per LUN, but not when you put a bunch of "pseudo SASI drives" onto a single storage card accessed via SASI.

The GIDE, and possible (direct) SDCard, interfaces should not have any such limitation.

Although, a 512M CP/M drive still has it's issues. Not least of which, it probably needs an 8000-entry directory which would take a long time to read on first access, let alone that that requires a huge amount of directory HASH space (32K). Also, addressing that much storage requires the use of fairly large allocation blocks, so there is more wasted space (esp. for small files).

Steven Hirsch

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Nov 25, 2020, 9:59:41 AM11/25/20
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On 11/24/20 9:43 PM, Douglas Miller wrote:
> It may be better to just access the SDCard "raw", but I thought I'd ask. FYI,
> CP/M 3 does not have the 8M partition limitation, it can support a 256M drive
> (partition). It just seemed that getting out of the fixed-size segment might
> be worth exploring.

CP/M 2 with ZSDOS (and other BDOS replacements) can also handle very large
partitions. Limit is 512MB, I believe.

Norberto Collado

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Nov 25, 2020, 12:04:44 PM11/25/20
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The original FW of the Z67-IDE was using 512MB for Drive 0 and drive 1 which gave best performance. There was a pushback to use the whole CF card and to use 512 bytes per sector to use all available storage space. That is when I added the BCD switches to define 128MB partitions and decided to use 512 bytes per sector, so two 256 bytes sectors are combined into one 512 byte sector. 

Should I go back to the original Z67-IDE code that supports only 512MB for drive? This will eliminate the need for the switches and allow to create a single partition from 8MB up to 512MB. You can only do a single partition per drive for CP/M and HDOS the same as when using a Winchester hard drive.

Thanks,
Norberto
It may be better to just access the SDCard "raw", but I thought I'd ask. FYI, CP/M 3 does not have the 8M partition limitation, it can support a 256M drive (partition). It just seemed that getting out of the fixed-size segment might be worth exploring.

Kenneth L. Owen

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Nov 25, 2020, 1:03:31 PM11/25/20
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Hi Norberto,

 

The Z67-IDE (and IDE+) use the switches for multisystem boots.  Unless there is a problem with the root data, if a system fails to boot, you can select another one which will boot and now have a way to recover the one that quit working.

 

  • Ken

 

Sent from Mail for Windows 10

 

Douglas Miller

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Nov 25, 2020, 1:04:35 PM11/25/20
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I'm not proposing any major changes. I simply thought that using MBR might make things easier. If not, then I think things should stay the same.

Norberto Collado

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Nov 25, 2020, 6:14:00 PM11/25/20
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Thanks for the feedback!

Norberto Collado

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Nov 28, 2020, 4:19:32 AM11/28/20
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Attached is latest Z67-SD PCB board. I made several changes based on feedback received and it looks better than before.

 

Thanks,

Norberto

 

From: "se...@googlegroups.com" <se...@googlegroups.com> on behalf of Norberto Collado <norberto...@koyado.com>


Reply-To: "se...@googlegroups.com" <se...@googlegroups.com>
Date: Wednesday, November 25, 2020 at 3:13 PM
To: "se...@googlegroups.com" <se...@googlegroups.com>

Subject: RE: [sebhc] New Z67-SD Controller

 

Thanks for the feedback!

Z67-SD-Controller _for_H8_H89.png

Joseph Travis

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Nov 28, 2020, 7:03:14 AM11/28/20
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Norberto,

Are there any thoughts on producing a version of this interface for the H-89?

Thanks,
Joe


To view this discussion on the web visit https://groups.google.com/d/msgid/sebhc/78A0FBA4-9B9B-484F-A206-4F5513B6998E%40koyado.com.

Glenn Roberts

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Nov 28, 2020, 8:00:45 AM11/28/20
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Joe: bottom line: this is a peripheral that works with both the H8 and H89!

 

Longer story:

 

Norberto is updating the design for his “Z-67” emulator.  The Z-67 was a large, heavy and expensive accessory for the H8/H89 that provided for an 8” floppy drive and an 11 meg hard (what they then called “Winchester”) drive.  The Z-67 was actually shown in catalogs (see below, Spring/Summer 1982) primarily as an H89 accessory at the time, but it can be used with either the H8 or H89.  Norberto reverse engineered the SASI protocols and implemented the same functionality on a single board.  His first generation of the device was in fact built on a card that could fit in the H8 chassis, or could be mounted externally in a 5-1/4” drive bay.  His second generation was smaller and mounts in a 3-1/2” bay.  They connect to the controller card in the computer via a SASI ribbon cable. Both those versions rely on Compact Flash drives as the solid-state storage medium.  CF devices are expensive and somewhat difficult to obtain so Norberto is moving to the more common Secure Digital (SD) card plus a simpler design with new display features as well.

 

To talk to the Z67-IDE device your computer needs a SASI controller card. Norberto designed a Z67 interface card for the ’89 in 2015 – looks like he may still have a few available…

 

http://koyado.com/Heathkit/H89-Z67.html

 

He has recently updated his design for the H8 interface board

 

http://koyado.com/Heathkit/H8-H17-H37-H67-USB.html

 

 

image001.png

Douglas Miller

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Nov 28, 2020, 8:37:50 AM11/28/20
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The terminology used here can be confusing. "Z67" might refer to the SASI interface board, plugged into an H8 or H89 (different boards). Or it might refer to the external cabinetry, power supply, SASI controller, and harddisk. Or some combination of those. Norberto (at al.) built a modern functional replacement for the (now rare and/or obsolete) external components. This was the Z67-IDE, then Z67-IDE+, and now (what I presume will be called) the Z67-SDC.

The SASI interface board is really just a parallel port specialized according to the SASI standard. The "SASI drives" are really the combination of a SASI controller board (lots of "smarts" - a CPU, firmware, etc) and one (or occasionally more) harddisk drives. SASI is the predecessor of SCSI, and has the same basic topology - very simple interface to the bus on computers (initiators), complex controllers on the peripherals (targets), high-level command structure to abstract-away hardware differences.

In theory, the Z67-IDE(+) would work on any computer (non-Heathkit) that has a SASI interface. It replaces the fragile and difficult to repair/replace controller+harddisk combination.

Norberto Collado

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Nov 28, 2020, 2:22:28 PM11/28/20
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WOW, $5999.00 back in the 80’s!!! Today’s price per CPI is $20,098.92. A lot of money.

 

Thanks Glenn on such great feedback.

 

Norberto

Norberto Collado

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Nov 28, 2020, 2:32:29 PM11/28/20
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SDC for “Secure Digital Card”? Yes, I can do that. Z-67 named was used to honor the Heath Z-67 external storage solution per add from Glenn’s previous email.

Glenn Roberts

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Nov 28, 2020, 3:06:48 PM11/28/20
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I think that’s just what “SD” stands for? Wasn’t implying anything special...

Sent from my iPad

On Nov 28, 2020, at 2:32 PM, Norberto Collado <norberto...@koyado.com> wrote:



Norberto Collado

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Nov 30, 2020, 1:55:22 AM11/30/20
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Here is the new link to the site of the Z67-SDC board.

 

http://koyado.com/Heathkit/Z67-SDC.html

Norberto Collado

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Dec 3, 2020, 10:35:08 PM12/3/20
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Douglas,

While reviewing the process to initialized an SD card from articles out of the web, I checked on the SDC prices and they are so cheap. I can get a 128GB SD for about $15.00 at Newegg.


There is no way I can use the 128GB storage range with current partitions. I was thinking that for this version of the controller, I should open the partitions to be 1GB per SCSI-1/SASI specs. So, that I can have at least 100 (1G) partitions with a 128GB SD card with 28GB spare for the HDOS Jukebox. I will add the check to avoid going above the 1GB range to eliminate the possibility of data corruption.

What do you think?

Douglas Miller

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Dec 4, 2020, 7:48:50 AM12/4/20
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Hi Norberto,

That sounds reasonable. Are you going to emulate SASI with 256-byte sectors, or 512? With 256 the SASI protocol can only address 512M (with 512 can address 1G).

Either way, 1G segments seems fine, even if half of that is inaccessible. I don't don't how available 2G, 4G, 8G, or 16G cards are, but those might suffer a bit of a loss by the larger segmentation. I'm assuming you'll just provide fewer segments in those cases, same as the CF card? I suspect we don't need to squeeze every byte out of a card, and that no one will likely need 16 segments, let alone 100.

Norberto Collado

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Dec 4, 2020, 1:13:32 PM12/4/20
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On this design I added a jumper that can be connected to a switch to select 256 or 512 byte sectors as I have been asked in the past for such feature.

Also added a another jumper to enable/disable the Jukebox HDOS library. So we can have CP/M/HDOS use the first .5GB and then the last .5GB can be used by the Jukebox library. 

I will proceed with the 1G partitions as originally defined by the SASI specs.

Thanks,
Norberto

Douglas Miller

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Dec 4, 2020, 7:10:47 PM12/4/20
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Just had a "hair-brained" thought... might be good to set that 256/512 switch well-recessed, so it can't be accidentally flipped. Or maybe even do something to embed the 256/512 setting on the media itself. I can't imagine a case where you'd want to flip that switch once you've put OS images on the disk. The drivers will need to know the sector size, I think. I can't imagine being able to switch on-the-fly without reinitializing software.

Norberto Collado

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Dec 4, 2020, 8:27:20 PM12/4/20
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Great feedback! I added an I2C NVRAM chip, so I can have that feature there.

 

NVRAM:

 

0x0000 = VD Settings (0-99)

0x0001 = 256/512 switch selection (0x00 = default = 256, 0x01 = 512 byte per sector.

0x…….   = tbd (future expansion)

Glenn Roberts

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Dec 4, 2020, 9:27:43 PM12/4/20
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I presume there will be port I/O access to read/write the NVRAM? (e.g.to query the sector size and other parameters)…

Douglas Miller

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Dec 4, 2020, 9:37:02 PM12/4/20
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Actually, I was thinking that the 256/512 setting needed to be on the (each) SDCard. For example one could make an image based on 512-byte sectoring and one for 256, whichever one is insert then gets the right setting. Otherwise, one has to label the card and remember to flip the switch.

But, that would require some hi-jinks to figure out where on the card to put it. So, not sure if it is practical. But, if it's worth pursuing perhaps the group can come up with a nice solution.

Norberto Collado

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Dec 5, 2020, 1:15:37 AM12/5/20
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I was planning to use the Serial Port for that, but we also can use SASI/SCSI-1 commands that are not commonly used to read/write a given NVRAM location via HDOS or CP/M.

Thanks,
Norberto
-------- Original Message --------
Subject: RE: [sebhc] New Z67-SD Controller
From: "Glenn Roberts" <glenn.f...@gmail.com>
Date: Fri, December 04, 2020 6:27 pm
To: <se...@googlegroups.com>

I presume there will be port I/O access to read/write the NVRAM? (e.g.to query the sector size and other parameters)…
 
From: se...@googlegroups.com <se...@googlegroups.com> On Behalf Of Norberto Collado

Norberto Collado

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Dec 5, 2020, 1:38:01 AM12/5/20
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OK, something like this, maybe:

NVRAM:
 
0x0000 = VD Settings (0-99)
0x0001 = SD#0 - 256 or 512 selection (0x02 = default = 256, 0x05 = 512 byte per sector.
0x0002 = SD#1 - 256 or 512 selection (0x02 = default = 256, 0x05 = 512 byte per sector.

To do this automatically by reading the SD card, a one sector will need to be reserved with such setting on the card; perhaps the last sector on a 1GB range, reserved and protected with the "2" or "5" value preloaded. I think this is overkill.

Using the NVRAM setup will be easier. Also I'm adding the LCD and I can display NVRAM settings such as; "SD0: 256, SD1: 512....", so the user knows which slot to use. Or we can use a HDOS/CPM SASI commands to display NVRAM settings, or use the serial port to query the configuration as well.

Thanks,
Norberto

-------- Original Message --------
Subject: Re: [sebhc] New Z67-SD Controller
From: Douglas Miller <durga...@gmail.com>
Date: Fri, December 04, 2020 6:36 pm
To: se...@googlegroups.com

Actually, I was thinking that the 256/512 setting needed to be on the (each) SDCard. For example one could make an image based on 512-byte sectoring and one for 256, whichever one is insert then gets the right setting. Otherwise, one has to label the card and remember to flip the switch.
But, that would require some hi-jinks to figure out where on the card to put it. So, not sure if it is practical. But, if it's worth pursuing perhaps the group can come up with a nice solution.

On 12/4/20 7:27 PM, Norberto Collado wrote:

Norberto Collado

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Mar 27, 2021, 4:39:19 PM3/27/21
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Updates on the Z67-SDC controller development:

 

HDOS

  • Boots HDOS at 2/4 MHz
  • Under OS it will switch fine to 8MHz and 10 MHZ.

 

CP/M-CP/M3:

  • Boots CP/M at 2/4 MHz
  • Under OS it fails to run at 8MHz and 10MHz.
  • CP/M hangs @2MHZ under stress test after +1hr. It is a random issue that I cannot find, as under HDOS it works fine.
    • Cannot continue development until this issue is resolved as it is a random issue that takes +1hr to surface.
      • I did check for stack corruption, but it is fine.
      • Interrupts are disabled when failure occurs.
      • The issue is that it reads the command from the H8, then it changes to the correct SASI Phase, and then it dies before sending any data to the H8. The watchdog kicks in and resets the Z37-SDC controller.
        • Once in the fail state, I can manually assert “REQ”, and when the watchdog kicks in, it recovers as it sends a check condition to retry command and continues to run the stress test until it fails again.
      • Slow Debug Process - WIP…

Added features:

  • Jukebox support to use .5GB of storage space. Thanks to Terry for finding that it was using only half of a .5GB.
  • Inquiry Command – Thanks to Terry for his support on this. It is still evolving.
  • 256/512 sector transfers. Selection is control by using the serial port and changes saved into the EEPROM.
  • SPI bus clock frequency selection. Selection is done under serial port and changes saved into the EEPROM.

 

Thanks,

Norberto

George Farris

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Mar 28, 2021, 4:50:20 PM3/28/21
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Hey Norberto if you are running this under CP/M3, try building a new image a couple K less in size.

George

Douglas Miller

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Mar 28, 2021, 5:40:40 PM3/28/21
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MMS CP/M 3 images are built for the full 64K space, I don't think Norberto has the experience to run GENCPM and change that.

I'm curious, what would leaving extra space at the top of memory give us?

George Farris

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Mar 28, 2021, 5:45:51 PM3/28/21
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I have a friend that built a hard drive out of an esp32 and an SD card.  He was running CP/M3 and ran into corruption issues at 62k he lowered the image to 60k and it has run fine now for weeks. 

It was just a thought, I don't really know anything about CP/M3.

George

Douglas Miller

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Mar 28, 2021, 5:52:23 PM3/28/21
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The problem Norberto is chasing is some timing issue inside the Z67-SDC. There is no problem on the Z67-IDE or (presumably) a Z67 with standard SASI drive. The OS does not crash in any of these cases.

Norberto Collado

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Mar 27, 2022, 11:11:51 PM3/27/22
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I think is time to revive the Z67-SDC controller. I have been thinking for a while (since March 28, 2021) in trying to understand the timing issue on the Z67-SDC board. I decided to add an 74AHCT123 to one of clocks as the HW is pulsing one of the clocks too fast and the H8 somehow misses it as it never replies that it was received. The main benefit of this board is that it uses SD media and parts are very inexpensive.

 

Hopefully we will have this board working properly soon.

Glenn Roberts

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Mar 28, 2022, 8:29:40 AM3/28/22
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I still have my 1.1 version of the original IDE board – 12 years old now!  A classic!  A redesign/update would be good and will keep things going for another 10 or more years!

 

  • Glenn

norberto.collado koyado.com

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Mar 28, 2022, 2:06:38 PM3/28/22
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Time goes pretty fast! Yes, that is a classic and I still have one in operation. I will revisit the idea of doing a redesign or update on such board.

Also, that was my first board and first-time using KiCad. 

Thanks,
Norberto
From: se...@googlegroups.com <se...@googlegroups.com> on behalf of Glenn Roberts <glenn.f...@gmail.com>
Sent: Monday, March 28, 2022 5:29 AM
To: se...@googlegroups.com <se...@googlegroups.com>

norberto.collado koyado.com

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Jul 25, 2022, 12:14:18 AM7/25/22
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After a year, finally I was able to run the Z67-SDc at 2/4/8/10 MHz at the HDOS OS level.  The timing issue was related to the signal /ACK. I was pulsing such signal at 1us. With Terry S. help, he created a small board to adjust such signal timing. Today I did made additional HW changes to the board created by Terry and adjusted the /ACK clock to 35ns. Finally this fix allowed me to boot HDOS without any issues and run at 10MHz.

 

I have been stressing the SD card all day and so far no issues reading or writing to it. Very stable.

 

Here is a picture of the working board. As I’m scrapping such design for a better one, at least I got it to work, and a lot learned when trying to emulate an SCSI IC in software.  

 

 

Thanks

Norberto

Glenn Roberts

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Jul 25, 2022, 5:39:26 AM7/25/22
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Great work guys! The original Z67 IDE was my first build when I got back into this hobby and was a game changer. From a capacity, speed, and reliability perspective suddenly the H8 was a powerful computer that I could use to do real work. I went on to build three Z67-IDE+ (second generation) devices. 

It is time to update the design. Looking forward to trying this third generation!

Sent from my iPad

On Jul 25, 2022, at 12:14 AM, norberto.collado koyado.com <norberto...@koyado.com> wrote:



After a year, finally I was able to run the Z67-SDc at 2/4/8/10 MHz at the HDOS OS level.  The timing issue was related to the signal /ACK. I was pulsing such signal at 1us. With Terry S. help, he created a small board to adjust such signal timing. Today I did made additional HW changes to the board created by Terry and adjusted the /ACK clock to 35ns. Finally this fix allowed me to boot HDOS without any issues and run at 10MHz.

 

I have been stressing the SD card all day and so far no issues reading or writing to it. Very stable.

 

Here is a picture of the working board. As I’m scrapping such design for a better one, at least I got it to work, and a lot learned when trying to emulate an SCSI IC in software.  

 

image001.png

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