About BOOM's perf. counters

Rafael B. Tonetto

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May 22, 2020, 6:02:27 PM5/22/20

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Hi,

I'm using the BOOM core to collect some perf. counters, but I noticed that the counters for the data cache misses are commented out in the core.scala file. I'm not sure on how to interface those pins with the external io signals. Which signals should I connect in the code in order to collect data cache misses? Or, maybe, isn't there a signal that I can read straight from the verilated code instead of relying on perf. counters?

Jerry Zhao

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May 22, 2020, 6:15:29 PM5/22/20

to Rafael B. Tonetto, riscv-boom

Hi Rafael,

Sorry, I forgot to reconnect these. I'll push a commit fixing this soon.

-Jerry

On Fri, May 22, 2020 at 3:02 PM Rafael B. Tonetto <rafael.bil...@gmail.com> wrote:

Hi,

I'm using the BOOM core to collect some perf. counters, but I noticed that the counters for the data cache misses are commented out in the core.scala file. I'm not sure on how to interface those pins with the external io signals. Which signals should I connect in the code in order to collect data cache misses? Or, maybe, isn't there a signal that I can read straight from the verilated code instead of relying on perf. counters?

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Jerry Zhao

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May 23, 2020, 6:21:41 AM5/23/20

to Rafael B. Tonetto, riscv-boom

Hi Rafael,

Here is a commit adding counters for L1 cache misses. Accessing these counters should be similar to Rocket.

https://github.com/riscv-boom/riscv-boom/commit/40668b9dac3ada52acaffe0ca6f01a0dae8981c3
This commit is based off BOOM master.

-Jerry

Rafael B. Tonetto

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May 23, 2020, 12:48:54 PM5/23/20

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Thank you very much!

Also, is there a way to estimate the penalty, in cycles, for branch mispredictions and for L1 cache misses (considering that there was a hit in L2)?

On Saturday, May 23, 2020 at 7:21:41 AM UTC-3, Jerry Zhao wrote:

Hi Rafael,

Here is a commit adding counters for L1 cache misses. Accessing these counters should be similar to Rocket.

https://github.com/riscv-boom/riscv-boom/commit/40668b9dac3ada52acaffe0ca6f01a0dae8981c3
This commit is based off BOOM master.

-Jerry

On Fri, May 22, 2020 at 3:15 PM Jerry Zhao <J...@berkeley.edu> wrote:

Hi Rafael,

Sorry, I forgot to reconnect these. I'll push a commit fixing this soon.

-Jerry

On Fri, May 22, 2020 at 3:02 PM Rafael B. Tonetto <rafael.bi...@gmail.com> wrote:

Hi,

I'm using the BOOM core to collect some perf. counters, but I noticed that the counters for the data cache misses are commented out in the core.scala file. I'm not sure on how to interface those pins with the external io signals. Which signals should I connect in the code in order to collect data cache misses? Or, maybe, isn't there a signal that I can read straight from the verilated code instead of relying on perf. counters?

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Jerry Zhao

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May 23, 2020, 2:59:05 PM5/23/20

to Rafael B. Tonetto, riscv-boom

Hi Rafael,

The branch mispredict penalty is 12 cycles.
A L2 hit incurs at least an additional 10 cycle penalty compared to a L1 hit.

-Jerry

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