The 80m transmit section of the Ver X2A transmitter has been built and, after a few modifications, is working considerably better than the X2 version did. It is putting 4 watts into a 50-ohm load, and the output waveform is looking cleaner, but not clean enough. The LM5134 does an excellent job of driving the final output FET: very sharp rise and fall times are evident on its output driving the FET gate. A little ringing is observed and some experimentation with a series resistor or ferrite bead should knock that down.
The two high-speed transistors driving the LM5134 are working adequately, but it was found that they are happiest operating at 5V instead of 12V. But they have one issue that is difficult to solve: they introduce some distortion to the 3.6 MHz signal due to slow rise/fall times, and the result is a significantly asymmetrical rectangular waveform instead of a square wave. The rise/fall times can be improved by lowering the values of the bias resistors, but that increases power consumption. Or the rise/fall times can be compensated for by pre-distorting the 3.6 MHz signal before it reaches the transistors, but that approach might require aligning each transmitter after it is built to ensure a square waveform.
A square waveform is essential in order to maximize the power at the fundamental frequency coming out of the power FET. Also, modeling suggests that the asymmetrical waveform is likely responsible for much of the distortion observed in the transmitter's output waveform. A straightforward no-align approach to generating a nearly perfect square waveform is to utilize a high-speed edge-triggered D flip-flop to divide the frequency in half, with each half of the flip-flop's output waveform corresponding to a rising (or falling) edge of the input signal. This could be done very easily in our transmitter because it is trivial to generate a 7 MHz signal using our Si5351 signal generator: the software need simply double the 80m frequency setting and use that to program the Si5351. That has been done, and tested, and shown to work.
But there is one issue. When the signal driving the flip-flop is turned off, there is a 50:50 chance that the output of the flip-flop will stop in the high state. If that were to happen then the power FET would be powered on continuously creating a DC short between power and ground. The power supply would shut itself down safely, but still that is an unacceptable condition. To avoid that issue, the flip-flop's CLEAR pin has been tied to the HF_ENABLE signal coming from the processor. So the processor can (and must) always set the flip-flop output low before it turns off the oscillator. This design should work, but it would be nice to have the circuit be inherently safe. Any thoughts on a more elegant solution are welcome!
73,
Charles