Octal bus transceivers

[Gavin]

Hello. I am designing a board with potentially long data lines (clock, data and latch). When messing about with matrix panels I have noticed that some of them have octal bus transceivers just after the input connector. Am I right in thinking that these effectively guard against voltage drops on long lines by boosting the signal?

I have read the data sheets but they make little sense to me in this context 

Gavin

[dafid...@gmail.com]

This link should help .. https://www.electronics-tutorials.ws/combination/bus-transceiver.html

The transceiver allows a multiple device bi-directional bus to operate.  It also buffers the signal it sends (ie provides relatively high driving current) and presents

a single device load to the signals it receives, reducing load on the bus (requirement for current).

V=IR implies that, as the bus driver needs to supply less current to the receiver, there will be less voltage-drop for the same resistance on your long wires.. so you can have a longer bus and stay within the signalling levels of the receiver.

****

Speculation/  looking for confirmation /

I **am pretty sure** the increased drive strength means a lower internal resistance from V-supply to the output of the driver. 

And **I THINK** that means that any stray capacitance along the bus are filled faster. 

Which should mean the rise-time of the bus-signals will be faster. 

And that means you can have a faster bus speed (clock) - or at least not be constrained by the rise-time to a slower clock 

(there are other constraints on clock speed of a bus that might be tighter than the bus rise time) 

[Tim Masson]

If you look at the TI  SNx4LS245 data-sheet it shows that the bus receivers are implemented with an hysteresis function, maybe a Schmitt-trigger circuit.  This gives an improvement on noise-margin which will reduce false triggering and data errors, which can be a problem when driving long lines, especially in low-power applications.  

These also provide a tri-state output,  which is much better than using an open-collector driver when a bus line is being used for bidirectional communications. By isolating the drive of unused sources the capacitive loading on the bus-wire is reduced, so the bus can work faster.

[Dave Spring]

And because you often daisy-chain the panels, so that the first panel only adds its own load and not adding the load of any cables and panels downstream.

In theory you should be able to drive a 5V panel from 3.3v logic, so  a rpi can drive one,

but I had to use a 74HCT245 to get a rpi to reliably drive 2 daisy-chained 32x64 P5 panels.

Dave

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[Richard Ibbotson]

As Dave Spring suggests the purpose of the buffers may not for line driving or receiving but for logic level conversion to allow later 5V CMOS logic to be driven by TTL or 3.3V logic. What is the part number of the transceivers? If they are HCT type then this is likely the case.

Richard

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On 14 Jun 2021, at 16:45, Dave Spring <dave....@gmail.com> wrote:



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[Richard Ibbotson]

ps

Making JLC PCB order tomorrow for 2 layer lead free. Client paying for DHL Express shipping If anyone has Gerbers ready to fly within those timescales.

Richard

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On 14 Jun 2021, at 17:30, Richard Ibbotson <richard....@btinternet.com> wrote:

As Dave Spring suggests the purpose of the buffers may not for line driving or receiving but for logic level conversion to allow later 5V CMOS logic to be driven by TTL or 3.3V logic. What is the part number of the transceivers? If they are HCT type then this is likely the case.

[Alex Gibson]

Hi Richard

 

Could you give me a cut-off time to email one to you please?  Might be able to take you up on this but only if several things go particularly well.

 

Kind regards,

 

Alex Gibson

 

+44 7813 810 765    @alexgibson3d    37 Royal Avenue, Reading RG31 4UR

 

admg consulting

 

edumaker limited

 

·         Project management

·         Operations & Process improvement

·         3D Printing

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[Richard Ibbotson]

Hi Alex,

Cut off time is hard 12:00 Noon tomorrow. Client deadline!

Cheers,

Richard 

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[Gavin]

Thanks all - having researched buffets and lime drivers it is becoming clearer. 

I already have a level shifter next to the MCU to do the logic level conversion from 3v3 to 5v (SN74AHCT125) but am concerned that having 16 downstream ICs (MAX7219) all sharing the same clock and latch lines and best case trace lengths for these two lines of potentially 2.5m, the circuit may need some additional help. 

Looking at data sheets, it looks like some SN74HC244 could do the trick and at ~20p each would not add significantly to cost, but

(i) in the absence of knowledge of how to calculate how many to put in, are there any pitfalls in just adding, say, one every 30cm / 2 ICs?

(ii) if it is more complicated than that, any pointers on how to approach the question properly greatly appreciated 

Gavin

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[Gavin]

I did, of course, mean buffers and line drivers!

[Richard Ibbotson]

I am thinking the major issues would be with capacitance and it’s effect on rise and fall times. 

What speed is your clock? And how do you daisy chain? Twisted pair? PCB? What capacitance per foot?

Richard

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On 15 Jun 2021, at 09:33, Gavin <gavi...@gmail.com> wrote:

I did, of course, mean buffers and line drivers!

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[Gavin]

Thanks Richard - the clock does not need to be high as the MAX7219s mean that the signals do not need to be continuously refreshed. So 10s of kbit/s maximum. The data line is daisy-chained from one MAX7219 to another from data-out of one to data-in of the next, but the clock and latch are provided to all as synchronised inputs. 

The connections are a mixture PCB traces (planning on 1oz / 35um thickness, scope to change trace width), and 22 or 24 AWG wire via Molex KK connectors. I’m not sure how I would calculate capacitance per foot.

Am I over-thinking this? It’s just that when I use online trace width calculators they suggest significant voltage drops over certain lengths

Gavin

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[Richard Ibbotson]

Hi Gavin,

Sorry I did not get back to you on this. My “major issue” should have said most significant effect so as not to be too alarmist!

The most significant effect of the 16 off MAX7219 and the long distance will most likely be related to capacitance and not resistance. You are working with clock and data transitions and have to meet their stability requirements. Limited current drive from the drying IC and high capacitance will contribute to slowing the transitions.

Working at 10MHZ clock give you immediate challenges. The MAX7219 requires 25ns setup of data before clock, and even though one might expect both data and clock to be similarly delayed then I would want to keep the rise times to less than 25nS since they may be asymmetric. Note also the output delay of the MAX7219 is 25ns, so the daisy chain length would be limited anyway at 10MHz with a common clock.

However if you are happy to work at say 50kHz clock then things are a bit more relaxed.

I don’t see an input capacitance specified for the MAX7219 so 8 assume 10pF, and  for 16 will be 160pF. For the wiring worst case would be something like twisted pair at 0.4 pF/cm, so another 100pF. Altogether a capacitive load of 260pF.

The HCT125 should be able to source and sink 6mA so rise and fall times would be of the order of 220ns I calculate (check my math!). You should be OK at 50kHz, rethink if you want to go faster.

Cheers,

Richard

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On 15 Jun 2021, at 15:57, Gavin <gavi...@gmail.com> wrote:

Thanks Richard - the clock does not need to be high as the MAX7219s mean that the signals do not need to be continuously refreshed. So 10s of kbit/s maximum. The data line is daisy-chained from one MAX7219 to another from data-out of one to data-in of the next, but the clock and latch are provided to all as synchronised inputs. 

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[Gavin]

Thanks Richard - really helpful. I am minded to incorporate some SN74HC244 to give me flexibility on clock speeds 

Gavin

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