A different kind of prototype board for RC2014

[Bill Shen]

There is already a RC2014 prototype board, but I want to try something different:

It is a 100mm x 100mm board with 39-pin RC2014 connector at the bottom.  The prototype area is for through-hole components.  What is different is the CPLD glue logic.  It is an Altera EPM7128, a medium-complexity 5V CPLD with 128 macrocells.  Part of the I/O are already prewired to RC2014 bus.  The remaining I/O are connected to 36 test pads, reset button, LED, oscillator, and an UEXT connector.   The 2x5 Altera programming header allow it to be reprogrammed hundreds of times.  The traditional address decoding logic will only take a small percentage of the CPLD logic.  It has enough logic to interface to LCD display, 8x8 LED matrix, I2C controller, SPI controller, Ethernet controller, etc.  This should keep me off the street all summer long!

[Olaf Dannath]

Very Nice Design, I planned something similar. Can I get the Board Files from you everywhere .

Thanks Olaf

[Jodie R.]

That's awesome!

Any concern about stress-relief?

[Bill Shen]

Olaf,
Attached is the Gerber files for the ProtoRC.  The boards were made by Seeed Studio.
  Bill

[Bill Shen]

By "stress-relief" do you mean the 100mm tall board supported only by the 39-pin connector?  A card guide would certainly be nice but many existing modules won't work with a card guide.  I think a nylon standoff somewhere in the middle of the board would keep it from shorting to the next board.
  Bill

[Jodie R.]

Hi Bill,

Yes, I was thinking of relieving the stress on the bus connector.  I could just see it getting bumped, or the inconsistent variable pressure from environmental air flow - it's a pretty good-sized lever.  A cage is the first place my brain went - I'm not a mechanical engineer, so half the time I suspect they're just pulling that stuff from... inappropriate places... but I still contemplate things I know they'll yell at me about. ;)

[Bill Shen]

My first project with the prototype board will be hosting a 4x20 LCD display which is fairly heavy.  I'm less worried about cracking the connector solder joints than the board leaning and shorting to the adjacent modules.  A nylon standoff or even a sheet of cardstock is adequate in the lab environment.  It'll definitely need better mechanical supports if it ever goes on road or takes a ride on a rocket.
  Bill

[Bill Shen]

First project with the prototype board: A 4x20 LCD display.

The hardware construction is straightforward.  The LCD display fits the prototype area almost exactly.  There is just room for contrast adjustment pot and backlight resistor.  The 3 control lines and 8 data lines go straight to test points T5-T15.  Very little wiring is required.

Run into a timing problem with LCD interface.  The LCD requires 100nS setup time and 300nS access time.  The Z280 bus is 12MHz or 83nS from clock to clock.  Each I/O access is 4 clocks and the WAIT signal is not available on RC2014 bus so I have to latch and stretch out the I/O access time in CPLD.  This is where all the extra spare logics and flip flops really become handy.

Wrote a quick assembly to print "HELLO World!!" on the LCD display.

  Bill

[phillip.stevens]

Run into a timing problem with LCD interface.  The LCD requires 100nS setup time and 300nS access time.  The Z280 bus is 12MHz or 83nS from clock to clock.  Each I/O access is 4 clocks and the WAIT signal is not available on RC2014 bus so I have to latch and stretch out the I/O access time in CPLD.  This is where all the extra spare logics and flip flops really become handy.

Wrote a quick assembly to print "HELLO World!!" on the LCD display.

Hi Bill,

Looks very nice!

Elm Chan (of FATFS fame) wrote a nice control system for the 44780 display protocol, which I've purloined, with the following interface.

It might be useful to provide a structured interface with (for example) a fuel gauge, bar graph, and pixel drawing capabilities.

Cheers, Phillip

[Bill Shen]

Phillip,
Thanks for the links.  Don't know what kind of controller is under the glob top encapsulation, but the timing does read like HD44780.  This particular display is text only.  I'm thinking of using one of Z280's DMA channel to drive it but that's probably overkill.  DMA is better suited for multiple 8x8 LED matrix which I hope to play with soon.
  Bill

[Olaf Dannath]

Thanks Bill,

I ordered a Bunch of it at JLCPCB. But I have to use another Surface finish Namen Enig. Because they toll me:

In the order info, you chose HASL as surface finish. But the holes are too narrow and we cannot make that for you since the tin of the holes is easy to connect together to cause the short circurt.

Now I Hope it will work.

Kind regards

Olaf

[Bill Shen]

Olaf,
Attached is a template of Altera design file with the pins already assigned.  (The assignment file is in top.qsf, you can also just import it to your project)

RC2014 already has reset button so you don't need to populate the reset button or the voltage supervisor (MCP130D or U8) unless you are using it for standalone operation.  You also don't need to populate the oscillator since RC2014 supplies the 7.37MHz clock (with jumper inserted from T37 to T38). 

You may notice the finger pads for Altera EPM7128SQC100 are extra long.  It is designed specifically for hand soldering, the large landing zone makes it easier to heat and apply solder by hand. 

Good luck and show us your prototype projects!

  Bill

PS, I welcome suggestions on how to make the protoRC better. 

[Bill Shen]

Interesting that we all want to reinvent a better wheel.  This is my version of SIO/2 on ProtoRC board.  All the I/O address selection logic are in the CPLD, so the wiring is directly from the CPLD's I/O to SIO/2 and wires from SIO/2 to serial adapters.  The CPLD is an overkill just to interface to SIO/2, so I plan to add I2C controller (PCF8584), SPI controller (inside the CPLD) to round out the signals for an UEXT (Universal EXTension) connector.  Probably will have logic left over for an array of 7-segment displays.

[Olaf Dannath]

Faster than I expected. The Boards had arrived from China to Germany.

[Bill Shen]

They look good.  The label says "HASL", so the pc board maker was able to use the HASL process after all?  You shouldn't have any problem with HASL finish.

Let me know you have suggestions for improvement.  I'm building up my 5th prototype boards just now and I have 2-3 more experiments I want to do, so I'm likely to use up all my boards fairly soon and ready for a design revision.
  Bill

[Nick Brok]

Hello,

Before soldering the SMD parts clean the pcb with isopropyl alcohol. I had some bad experience with Chinese PCB's while using smd components. The solder didn't flux enough.

Nick de PE1GOO

[ZO...@gladucalled.com]

Hi Bill,

Would you please take at my post here.

https://groups.google.com/forum/#!topic/rc2014-z80/KGC9QcfmiSk

I am looking for RC2014 PCB layout specs - ballpark sizing information.

Thanks,

=SteveM.

[Olaf Dannath]

Thanks for your advice, Nick . I will try to clean the boards very well.

[Olaf Dannath]

Hello Bill,

the voltage supervisor. For which voltage did you use on your board?

Olaf

[Bill Shen]

Olaf,
It is MCP130-460DI/TO 4.475V supervisor, Jameco part number 1284957.  It is not necessary to install it if you are using the prototype board with a RC2014 bus.  If you do install it, it has an open-collector output so will work with the existing reset circuit in parallel.  However, you'll notice a longer delay before reset is letting go because MCP130 holds reset for about 350mS.
  Bill

[Samster]

Hi Bill - would be interested to know how you get on with the PCF8584. I couldn't get mine to release the I2C bus without inserting an extra dummy write to the PCF8584 register. I haven't got round to investigating if this is a bus timing issue with my code/xtal choice or if it's just me not being able to follow a datasheet anymore!

[Bill Shen]

It is on my to-do list, I just haven't got around to it.  I have all the parts already: PCF8584 controller and test parts: PCF8574 I/O expander and AT24C256 EEPROM.  I'll push it up the to-do list and see if that'll get done any sooner ;-)
  Bill

[Samster]

No hurry, it took me two years on-and-off to get mine working reliably ;-).

Out of interest, what took you down the EPM7128 route? It fits very well real-estate wise on your board, and although I've bought enough soldering iron parts to attempt my first surface mount soldering, I've not been brave enough yet to try them out. I've been chicken so far and have used ATF1504AS in a through hole PLCC socket for my first attempt at a RC2014 module. For my next project I was trying to figure out how to fit a PLCC 84 socket onto the standard module footprint  for the ATF1508AS :)

[Bill Shen]

I like the Altera toolset because it is easy to use and its programmer is cheap.  Through trials & errors I found EPM7128SQC100 the best fit for 5V microprocessor designs.  It is lesser than $5 each in quantity of 10 so I bought a few lots and use them in all my designs.  The lead pitch is 0.65mm which is not difficult for hand soldering under microscope.  A prototype board is a good way to practice SMT soldering: you only need to get the power, ground and 4 programming lines correctly to use the device.

The standard RC2014 format (50mm x 100mm) is too small for CPLD designs.  100mm x 100mm is too tall & wobbly, I think a 75mm x100mm format is about right.
  Bill

[Bill Shen]

Samster,
Could you elaborate on where the extra dummy write is needed to release the I2C?  I breadboarded the PCF8584 and used an Atmel 24C256 serial EEPROM as the test device.  I just follow the flowcharts in PCF8584 datasheet and all seems to work.  There is a dummy read required when PCF8584 is initially configured in master receiver mode but that's well documented.

  Bill

On Sunday, June 10, 2018 at 9:43:23 AM UTC-6, Samster wrote:

[Samster]

In master transmit final step is to tell the PC8584 to generate the STOP condition - but I find the I2C is not released unless an extra write to the S0 register is written directly after:

    LD A, PCF_PIN | PCF_ESO | PCF_STO | PCF_SACK ; 0xC3
    OUT (PCF8584_CSR), A; S1
    OUT (PCF8584_DAT), A; BB does not go high unless S0 gets a write after STOP

Similarly in master receive I had to write to S0 ahead of generating the STOP condition. This also meant I had to rearrange reading the final byte before generating STOP (otherwise my dummy write corrupts the final byte in S0).

    IN A, (PCF8584_DAT) ;
    LD (DE), A

    LD A, 5 ; dummy address "2 << 1 | 1"
    OUT (PCF8584_DAT), A; dummy write to S0 release bus

    LD A, PCF_PIN | PCF_ESO | PCF_STO | PCF_SACK; 0xC3
    OUT (PCF8584_CSR), A; S1

If I don't do the above, the first read or write works as expected, but because but I2C bus is not released, the next read/write blocks waiting for BB.

I'm not sure if I'm breaching this constraint in my code, I haven't checked the timing in enough detail yet:

"A minimum of 6 clock cycles must elapse between consecutive parallel-bus accesses to the PCF8584 when the I2C-bus controller operates at 8 or 12 MHz"

[Bill Shen]

Samster,
Thanks for the detailed description.  I didn't have the problem of PCF8584 not releasing the I2C bus after STOP.  I verified that with the scope and I can do consecutive reads of blocks correctly.  The bus speed is 7.37MHz so I think that means a minimum of 3 clock cycles between consecutive parallel-bus accesses.  My initialization routine looks like this:

    ld a,80h        ; load byte 0x80 into reg S1' so next byte will
    out (regS1),a    ;  be loaded into reg S0'.  serial interface off
    ld a,55h        ; load byte 0x55 into reg S0', effective
    out (regS0),a    ;  own address becomes 0xAA
    ld a,0a0h        ; load byte 0xA0 into reg S1 so next byte will
    out (regS1),a    ;  be loaded into the clock control reg S2
    ld a,18h        ; load byte 0x1C into reg S2, system clock is 8MHz
    out (regS0),a    ;  SCL frequency is 90Khz
    ld a,0c1h        ; load byte 0xC1 into reg S1; reg enable serial interface
    out (regS1),a    ;  set I2C bus into idle mode, SDA and SCL are high
            ;  the next write or read will be to/from transfer reg S0

What device were you using to test your PCF8584?  I used a serial EEPROM, Atmel AT24C256.
  Bill

[Samster]

I've used various devices (HT16K33, DS3231, MCP2308, ATTINY45,  SSD1306), the bus stays locked with all of them which led me to believe it was the PCF 8584 not releasing. I tried various different pull up values without any significant changes in behavior. I saw the same behavior on my breadboard and the PCB module I had made up from OSH park. I also tried swapping out PCF8584 chips (although they were both sourced from the same ebay store), I may try to source some alternatives.

I'm also using 7.37MHz.

I've ordered a AT24C256 to experiment with.

This is my init routine - it includes flipping a 1-bit register (PCF8584_RST at address 0xC2) in my CPLD to cleanly reset the PCF 8584 (and SSD1306). The values written to S1 (PCF8584_CSR at 0xC0) and  S0 (PCF8584_DAT at 0xC1) seem to match yours.

8514:             I2C_INIT:
                 
8514: F5              PUSH AF
8515: C5              PUSH BC
                 
                      ; reset PCF8584 with delay
8516: 3E01            LD A, 1
8518: D3C2            OUT ( PCF8584_RST ), A
                 
851A: 010000          LD    BC,0
851D:             I2C_INIT_SLEEP:
851D: 10FE            DJNZ    I2C_INIT_SLEEP
851F: 0D              DEC   C
8520: 20FB            JR    NZ, I2C_INIT_SLEEP
                 
8522: 3E00            LD A, 0
8524: D3C2            OUT ( PCF8584_RST ), A
                 
8526: 3E80            LD    A, PCF_PIN
8528: D3C1            OUT (PCF8584_CSR), A
                 
                      ; set own address
852A: 3E55            LD    A, I2CID_Z80
852C: D3C0            OUT (PCF8584_DAT), A
                 
                      ; set clock (8MHz CPU clock) into S2
852E: 3EA0            LD    A, PCF_PIN | PCF_ES1
8530: D3C1            OUT (PCF8584_CSR), A    
8532: 3E18            LD    A, PCF_CLK8 | PCF_TRNS90
8534: D3C0            OUT (PCF8584_DAT), A
                 
                      ; enable i/f
8536: 3EC1            LD    A, PCF_IDLE
8538: D3C1            OUT (PCF8584_CSR), A
                 
853A: C1              POP BC
853B: F1              POP AF
                 
853C: C9              RET

[Bill Shen]

The SSD1306 is pretty interesting.  I ordered a few to play with.  I'll do more testing with an I2C I/O expander, PCF8574.  I don't have a Z80 processor right now (hopefully that'll change in a few weeks) and I'm driving the PCF8584 with a Z280 processor which does not have the same bus timing as Z80.  That may be the difference.  I'll take some timing measurements and see how that matches with the datasheet.
  Bill

[Bill Shen]

Received rev1 of prototype board this afternoon.  It measures 100mm x 76mm and is not quite as wobbly as rev 0 prototype board.  It still builds around the EPM7128 CPLD, but the prototype area is more defined than the rev 0 board.  A number of functions are pre-defined:

The top area is six 7-segment displays.  It will be fully populated with 7-segment displays as bus monitor module but partially populated for other designs and serves as visual indicators

The middle area has connectors area in the front, 35 columns of connected pads for 300mil and 600mil, enough space for TMS9918 + RAM, paged ROM + RAM, Z80 or other 8-bit CPU.  The back is set aside for a Compact Flash adapter.

The bottom area is the CPLD, clock, voltage supervisor and RC2014 connector.  The CPLD interfaces to RC2014 bus and provides glue logic for devices in the prototype area.

I have a dozen specific designs I want to implement on this rev 1 board.  I'm excited about one specific kind of prototype which is experimenting with other 8-bit microprocessors such as MC68xx, 6502, 8051 or even 16-bit uP with 8-bit bus such as MC68008 and NS32008. 
  Bill

[Bill Shen]

The first prototype is to check out the board design.  There is just one jumper from RC2014 clock to the on board clock.  The seven-segment displays are showing the hour-minute-second values of the Z280RC real time clock.  The design consumes 75% of the logic because CPLD logic is fetching the data from its internal registers and driving the 7-seg displays constantly.  Z280RC is not doing anything other than updating the time value once a second.  The rev 1 prototype board is working as designed.  Attached is the schematic and gerber files.
  Bill

[Bill Shen]

The next prototype project is a simple serial port.  Altera EPM7128 contains 128 macrocells which is complex enough to do a simple serial port.  There are very little external wiring: just hook up T1 as transmit, T2 as receive, and connect RC2014 clock to on board clock.  One of the 7-segment display is used as visual indicators of the serial port internal states.  Most of the design is inside the CPLD:

• Fixed serial protocol of 115200 baud, 8 bit data, no parity, 1 stop bit, no handshake
• Receiver has a data buffer, transmitter has no data buffer.
• Fixed I/O addresses: 0xF8 for status/command register, 0xF9 for transmit/receive data
• Status bit 0 is Transmit Empty, status bit 1 is Receive Ready, status bit 2 is transmit interrupt enable, no status for error conditions.
• Fixed interrupt vector, 0xF8, for Mode 2 interrupt.
• Receive interrupt always enabled, transmit interrupt enabled by writing 1 to bit 2 of command register (0xF9).
• 120 out of 128 macrocells (94%) are used.

The fixed I/O addresses and interrupt vector seem a serious limitation, but since this is a programmable device, the values can be easily changed to other values.  The upside of everything being fixed is the serial port is ready to use after power up, no initialization is required. 

Unfortunately I ran out of logic, otherwise it would be very cool to have the serial data DMA into RAM memory, release reset to Z80 and boot off the RAM and then program the flash EPROM.  No more tedious ROM programming.
  Bill

[Bill Shen]

Ed Brindley's sound card re-implemented in the prototype board.  All the TTL logics are consolidated in the CPLD which reduce the number of wiring significantly.  Altera Quartus tool has an extensive TTL library, so Ed Brindley's original schematic was redrawn using the equivalent TTL library components and look very much like the original schematic.  Only a small fraction of the CPLD is utilized.
  Bill

[Marten Feldtmann]

That is a great idea - but I would not be able to soldier the CPLD on the PCB :-(

[Bill Shen]

Unfortunately CPLD is generally available only in surface mount package.  Some were available in PGA package in the early days but these were extremely expensive.  There is a version of Altera 7128 still available as 84-pin PLCC (EPM7128SLC84) and 84-pin PLCC through-hole socket is readily available. 
  Bill

[Marten Feldtmann]

Yes, I looked at mouser and there are other PLCCs available (even in PLCC44). The device you mentioned is at its end of life. What programmer can be used to program Intel/Altera stuff ?

Marten

[Michael Cullen]

You can get Altera programmer clones on eBay easily enough.

You could probably convince openocd to use another jtag  programmer to do the job as well if you got Quartus (the intel design tool) to output the right file (svf I think?) I’ve used openocd with the Altera programmer before this way.

I use the Altera programmer clone because it means i can program directly from Quartus which makes things a bit easier.

By the way I’ve been using the EPM7032 part in PLCC44 format because it’s socketable. I did use the EPM3032 but they discontinued that- the 7032 is basically the same pinout though.

Michael

--
You received this message because you are subscribed to the Google Groups "RC2014-Z80" group.
To unsubscribe from this group and stop receiving emails from it, send an email to rc2014-z80+...@googlegroups.com.
To post to this group, send email to rc201...@googlegroups.com.
To view this discussion on the web, visit https://groups.google.com/d/msgid/rc2014-z80/f53a93af-c8ed-48c4-b1fe-0a70acb6e6f0%40googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[Bill Shen]

EPM7032 is more than adequate to replace the TTL logic in the sound board.  It is not enough, however, to replace the TTL logic in the 512K ROM/RAM board.  The 7064 is also available in 44PLCC package, it may be adequate to replace the logic of 512K ROM/RAM, so yes, 44 PLCC may be a good alternative to the 100-pin QFP; it is certainly easier to solder.

The 7000 family was introduced in early 1990's, so it is no surprise they have reached the end of life (like most of the parts of retro computers).  It was a very popular family, however, so parts are still available in grey market, and quite cheaply.  I bought several trays of EPM7128SQC100 cheaply and use them in just about all my designs.  I must have used 100+ of them already and have not encountered any problems with the part itself.

This is 512KROM/RAM with the TTL logic replaced with about 30% of a EPM7128.
  Bill

[Mark T]

Memory management of 512K ROM/RAM board is mostly not used by RomWBW. Top 32K of z80 address space is always a fixed area of RAM. Low 32K of address space is set as two 16K blocks for the 32K, you could provision a 5 bit latch that will only respond to the low 16K page select write register of the memory management, but use that to select between RAM and ROM and select  one of 16 of 32K pages. It could be software compatible with RomWBW with greatly simplified logic. This could also be done quite easily with TTL without the 74HCT670s.

Mark

[Alan Cox]

On Thu, 27 Sep 2018 at 00:01, Mark T <mark...@gmail.com> wrote:
>
> Memory management of 512K ROM/RAM board is mostly not used by RomWBW. Top 32K of z80 address space is always a fixed area of RAM. Low 32K of address space is set as two 16K blocks for the 32K, you could provision a 5 bit latch that will only respond to the low 16K page select write register of the memory management, but use that to select between RAM and ROM and select one of 16 of 32K pages. It could be software compatible with RomWBW with greatly simplified logic. This could also be done quite easily with TTL without the 74HCT670s.

That's basically what is supposed by the Retrobrew/N8VEM SBCv2. It's
fine for CP/M including banked CP/M 3 but does mean it'll never be
able to run fun stuff like MP/M usefully. It was more conventional in
the olden days to switch the low 48K or 56K as one - which is what the
OS's expect but I think breaks ROMWBW 8(

I don't know how hard it would be to have top 16K fixed, low 32K paged
using the bottom bank register and the 8000-BFFF range either fixed or
paged with the 32K according to a spare bit somewhere. That could then
work with everything (I think).

Alan

[Bill Shen]

I see, now I know why you use 74LS173 to select 32K pages in your Z80SBC design instead of the 16K page size of 512K ROM/RAM.  A small CPLD like EPM7032 should be able to consolidate all the TTL logic and even change the page size to 16K as Alan has mentioned.  I see Phillips Stevens is working on MPM so perhaps 16K page size will be useful after all.
  Bill

[Mark T]

I don't think it makes sense to try and achieve what Alan described with discrete logic. It would probably be a higher chip count than the existing 512K ROM/RAM module.

With cpld it might be possible to reduce the logic to fit it in a smaller cpld. Probably a 5 bit register for the low 32K and a 6 bit register to select the 16K from 8000 to BFFF.

I didn't realise how simple the use of the 512K ROM/RAM by RomWBW was until I made the mods to hbios and got it working quite easily in only 512K RAM. I didn't order boards yet as I wanted to include a couple of other boards to share the shipping cost, but I don't think I have space to include traces to the extended address bus and allow the RAM to be expanded to 1M.

Mark

[Phillip Stevens]

Bill Shen wrote:

I see Phillip Stevens is working on MPM so perhaps 16K page size will be useful after all.

Yes, whilst a first MP/M for RC2014 would be a non-banked version on the 64kB RAM board, it would be great to have a 48kB bankable or 3x 16kB bankable RAM version.

The 32kB banks are a bit limiting for MP/M.

MP/M prefers 16kB Common, and 8x 48kB banked. This is quite easy to do with a Z180, and I dare say also with Z280 too.

But, I don't think there is any RC2014 memory board around today that supports this configuration exactly.

There's no need for any special ROM support, as MP/M is commonly loaded from standard CP/M (which can be in ROM or otherwise).

The attached MP/M brief has a nice picture of what's required.

I don't know if anyone is interested in building such a RAM module for the RC2014?

Let me know if you are, please. I know what I would do with it.

Cheers, Phillip

[Alan Cox]

On Thu, 27 Sep 2018, 06:53 Phillip Stevens, <phillip...@gmail.com> wrote:

Bill Shen wrote:

I see Phillip Stevens is working on MPM so perhaps 16K page size will be useful after all.

Yes, whilst a first MP/M for RC2014 would be a non-banked version on the 64kB RAM board, it would be great to have a 48kB bankable or 3x 16kB bankable RAM version.

The 32kB banks are a bit limiting for MP/M.

MP/M prefers 16kB Common, and 8x 48kB banked. This is quite easy to do with a Z180, and I dare say also with Z280 too.

But, I don't think there is any RC2014 memory board around today that supports this configuration exactly.

The 512K board does because it has individual control of each 16K so you just pin the top 16K and flip the others together. You get 10 48K banks a 16K common and 16K left over - so you could certainly do 6-8 48K banks plus a RAM disc.

Alan

[Phillip Stevens]

 Phillip Stevens wrote:

MP/M prefers 16kB Common, and 8x 48kB banked. But, I don't think there is any RC2014 memory board around today that supports this configuration exactly.

 

Alan Cox wrote: 

The 512K board does because it has individual control of each 16K so you just pin the top 16K and flip the others together. You get 10 48K banks a 16K common and 16K left over - so you could certainly do 6-8 48K banks plus a RAM disc.

Thanks. That's good to know.

I hadn't investigated this fully, and damn one more excuse to procrastinate just vaporised. ;-) 

Phillip

[Bill Shen]

Z280's page size is 4K, so it will work well with MPM's memory banks.  ZZ80RC is a Z280 SBC with 512K of RAM and CP/M2.2 already ported to it, so potentially it can transition to MPM quite readily.  I designed it as hobbyist-friendly (all through-hole components) and released the design files to the public, so hopefully someone would build it and port MPM to it.
https://www.retrobrewcomputers.org/doku.php?id=builderpages:plasmo:zz80rc
https://groups.google.com/forum/#!topic/rc2014-z80/dOymr7Q4p6M

The 512K ROM/RAM board does support 16K page but it is rather expensive because of the 74LS670.  I think it is possible to cut the price by half or more by consolidating all TTL logic into a low-cost CPLD.

  Bill

[Bill Shen]

Rewrite the ZZ80RC BIOS and added a 8-bit CF interface.  The interface logic is surprisingly simple.  The 8-bit wide interface is less noisier than 16-bit so termination resistors and RC filter are not necessary.  I'm able to interface to a wide varieties of CF disks.  Out of 20 different CF disks, the CF disk in the picture is the only one I can't reliably read/write.  This is a good prototyping exercise, I now believe I can add a CF interface to ZZ80RC using all through-hole components and still keep it at 50mm x 100mm.
  Bill

[Mark T]

Hi Bill,

Does the z280 have a clocked serial interface similar to the z180? I've seen a few z180 designs using this to interface to sdcard via spi, doesn't seem to add many components but based on what I've seen in RomWBW needs to swap the order of the bits from A7 to A0, A6 to A1 etc. RomWBW seems to use a 256 byte look up table so its not too big an overhead, possibly better than bit banging.

Actually cpld might be a good way to interface sdcard to z80, but I think I'll stick with ttl shift registers for now even though it does fill a 100x50 module.

Mark

[Alan Cox]

> Actually cpld might be a good way to interface sdcard to z80, but I think I'll stick with ttl shift registers for now even though it does fill a 100x50 module.

There are a couple of CPLD designs around: The ZXSPI is meant for the
Sinclair spectrum systems generally
http://spectrum.alioth.net/doc/index.php/ZX_SPI has the verilog for
it. It's a bit ugly in some ways as it uses 16bit decoding to cope
with the sinclair systems but that looks fixable

There's also an off the shelf (if you can find someone making some atm
anyway) SPI board that plugs into any Z80 socket and the CPU sits on
the board. It steals ports 1F and 3F for SD card but works with pretty
much anything with a socketed CPU.

[Bill Shen]

The Z280 UART is not capable of synchronous serial mode.  You can operate it at x1 clock mode and send the clock along with the data, but you'll need to strip off the START and STOP bit. 

CPLD is the way to do SPI.  I saw your SD card design on another thread, I'll port it to CPLD and try it.

  Bill

[Bill Shen]

Can't sleep--my dog just had surgery and he is in pain, so I stayed up to keep him company and ported your SD card design to CPLD.  I forgot how much a pain it was to do state machine with TTL logic.  I like the way you used the 74163.  With the CPLD approach, I wouldn't bother with external I/O address jumpers--just hardwire the CPLD with the specific address.  Most of the circuits fitted in the CPLD, but I will need to add an external 5V-to-3V voltage shifter for SD_CLK, SD_MISO, SD_MOSI and a 3.3V LDO regulator.

I ordered a few SD card adapters, I want to try this design out on my prototype board.

  Bill

[Mark T]

Hi Bill,

Maybe on proto board its easier to use one of those breakout boards that includes the level shifters and regulator. I'd considered that myself but wanted to avoid too many breakout boards in my system as it can look a bit messy.

I'm very interested to hear how it goes, I'll feel a bit guilty if I messed up the logic and you end up being first to test it, but as its cpld I guess its not such a big problem to include corrections. I think China is on holiday to the 9th so its probably at least two weeks before I get any boards, probably longer as I'm looking at some of Alan's suggestions and have another couple of board designs in process that I might group into one order.

Will the cpld input leakage allow the card detect using the /cs line from sd card to work? Internal pull up in the card is typically 50K but could be between 10K and 100K on the sdcard spec I looked at.

regards,

Mark

[Mark T]

Hi Bill,

I think I spotted an error in the logic of my schematic. ENT on the 74HCT163 must be logic high to allow counting.

It could just be tied high, but I'm thinking it might be connected to /SER_WR then U7A could just be an inverter instead of NAND. This gives me a greater choice for U7 to be Inverter, NAND or NOR.

I'll update schematic in my thread on the SD card module when I finalise a few revisions.

Mark

[Bill Shen]

Mark,
Thanks for the update.  I'm too old to pull an all-nighter!  When I've recovered, I'll run a simulation of the design and also program the CPLD and check it out with real hardware. 

Leakage current of CPLD I/O pin is specified at 40uA, max, so 50K pull up is barely sufficient to pull it above logic 1.  I can augment the open collector driver with CPLD's internal pull up which is nominally 50K, I think.
  Bill

[Mark T]

Bill,

Using the pull up from the cpld would prevent using the pull up of the sdcard to detect it is present. It wouldn't be essential to test the interface but seemed like a nice thing to include so I use a 74hct125 input wuth 470k pull down on /CS and a separate open collector drive to pull /CS active low. To do this with the cpld you probably need a high impedance buffer to the cpld input with a separate open collector output from cpld to pull it active low.

I have some other changes to improve the speed for reading blocks from the sdcard, I'll post schematic in my sdcard module thread when I finish trying to reduce the chip count. What I'm adding is a second address for reading data, this second read address will also trigger another transfer, so it should be possible to use INIR.

Something like:-

    LD    HL,BUF

    LD    BC, 00xx      ; xx = read + transfer address

    INIR

    DEC    B

    INIR

    DEC    C               ; point to read only address

    INI

Still a work in progress but I think it should work.

Mark

[Bill Shen]

Mark,
You are right that pulling up the CPLD won't work, don't know what I was thinking.  I'll probably put 2N2222 transistor front end to detect high impedance input.

I don't have much time today but I thought I show you a couple pictures I captured on scope this morning before I go:  The top trace is SD_MOSI and the bottom trace is SD_CLK.  First picture is writing 55 to data port and 2nd picture is writing AA to data port.  The logic is clocked by RC2014's 7.37MHz.  The state machine is injecting the long idle period before the SD_CLK starts.

If I looping back MOSI to MISO, I'm able to read what I wrote, so the receiver is working.

  Bill

[Mark T]

Hi Bill,

Looking good, seems to confirm the state machine logic is correct.

The delay prior to the fist clock pulse may seem long, but I think that includes the end of the write to output port.

The next critical part of the timing but be the last of the clock pulses relative to the end of the read from the input port to see that the data is stable at the end of the read. You see the correct data read so I think its working.

Its going to be some time before I catch up with hardware, I really appreciate the effort you've put into this.

I'm not sure how much further you were intending to take this, but I was thinking RomWBW would be my target for implementing this, as it looks like RomWBW already supports the sd card protocol and I'd only need a small alteration to the hardware level interface.

Mark

[Bill Shen]

I'm waiting on the SD breakout board so it'll be 2-3 weeks before I can test it with a real SD card.  I'm testing the SD prototype with my ZZ80RC, I don't have ROMWBW ported for it.  I'll need to figure out how to talk to SD card and put the driver in CP/M 2.2 BIOS.  As an alternative, I can figure out how to port ROMWBW to ZZ80RC--probably a better approach...

A couple questions:  What should be the default port address for this card?  What is the clock speed of the SD_CLK?  Thanks,

  Bill

On Saturday, October 6, 2018 at 11:16:42 PM UTC-6, Mark T wrote:

Hi Bill,

[Mark T]

Hi Bill,

I tried posting my changes to hbios of RomWBW in my SBC CPM thread but getting an upload error to try again later, maybe it doesn't allow upload of zip files, its only 245K.

RomWBW has a lot of build options but not too difficult to figure out, my example might help you build a 384K RAM image which has 256K "Preloaded RAM drive and 128K user RAM drive. I added a new platform definition PLT_MT to track my changes and its probably the easiest way to add support for ZZ80RC. There are already platform options for Z180 so that might help guide changes required for Z280.

If you download RomWBW to your local drive, Windows only I think, and verify it builds by following the readme files in the Source directory, then you could replace hbios folder with my zip version and it should rebuild OK.

I didn't choose a default address yet, using switches to allow selection later. I'll try and find time to look through Steve's address selection spreadsheet again. Probably pick on the doesn't overlap Standard RC2014 ports, avoid the bitbang spi ports and avoid Sord M5 IO ports.

SD_CLK should run at the same clock speed as Z80 CLK, IN A,(nn) is 11 clock cycles and IN A,(C) is 12 clock cycles on Z80. Check if Z280 has enough clock cycles to work with the state machine. Looking around at various internet pages seems to show the sdcard spi clock should run at up to 25MHz, so I was hoping to get it running on a 20MHz Z80 clock, but planning 7.932MHz for starters.

Mark

[Bill Shen]

This is prototype of Z80SBCRC built on a rev1 ProtoRC board.  It is a ROMless design with banked 512K of battery-backed RAM for memory.  Each bank is 16Kbytes with the top 16Kbyte as the fixed, common memory.  All random logic is contained in the Altera EPM7128 CPLD.  A 8-bit compact flash interface provides the mass storage for CP/M.  It interfaces to the standard RC2014 bus.  It is designed for 20MHz Z80 operation (22MHz actual).

Since there is no ROM on board, there needs to be a way of loading program in RAM initially. This is accomplished by putting the board in the "serial bootstrap" mode via a jumper selection. In this mode, Z80 bus is tri-stated immediately after reset, the serial port waits for incoming 255 data at 115200,N,8,1 and place the data in RAM starting from location 0x0 to 0xFF. When the 255th byte of serial data is received, the bus mastership is relinquished back to Z80 and it begins program execution at 0x0, just like a normal power-on reset. Once program is loaded, the mode jumper can be changed to "RAM bootstrap" mode where the Z80 will boot from location 0x0 of RAM normally.

SCMonitor has been ported to Z80SBCRC as well as CP/M2.2. 

I ran the The ASCII mandelbrot benchmark with MBASIC80 in CP/M 2.2 which took 52 seconds to complete.  That is the expected performance for a 22MHz Z80. 

Design information of Z80SBCRC is on my GitHub page, https://github.com/Plasmode/Z80SBCRC

[Steve Cousins]

Very nice Bill

[Bill Shen]

Got banked CP/M running.  My first CP/M 3 porting experience.  Did a lot of readings and asking lots of questions, but the resulting code is actually pretty small.  One reason is I let GENCPM do most of the works, that was a pretty smart software for early 1980's.
  Bill

[Bill Shen]

Sent off three board designs to Seeed Studio.  One of them is Z80SBCRC.  It is in the standard RC2014 format, 50mm x 100mm, although it will be be 50mm x 150mm when the compact flash adapter is soldered to the edge connector.
  Bill

[Bill Shen]

I used up my lots of prototype boards doing various projects; instead of re-ordering, I just design a different one.  This is a through-hole prototype with Altera EPM7064S, which has enough logic to address decode the RC2014 bus as well as the random logic needs of a specific design.
  Bill