Hmm, double the memory?

[Robb Bates]

I was just looking at the schematic for Spencer's 512K RAM/ROM board.  I noticed the '139 U5A has two unused outputs.

Which made me wonder if I were to piggy back solder two more chips on the RAM and ROM (or two ROMs or two RAMs), wire the bent out CE pins to /Q2 and /Q3, and do a little bit of tweaking in the BIOS code to change/expand the assigned memory, couldn't we easily add another 1MB of RAM and/or ROM to this memory card?

For the ROM, I might have to split and burn two halves of the generated BIOS code in order to have it work correctly.

Robb

[Robb Bates]

Digging more into  Dr Scott Bakers' ROM/RAM Module and  Sergey Kiselevs' Zeta 2 boards, it looks like that's exactly what it's designed to do.  Well, they look like they're trying to add two more RAM chips, but I think I'd prefer to add more ROM to grow the ROM disk capacity.  I think that just means some tweaking in the BIOS code to assign the right banks.

I'll have to wrap my head around that part of the code (HBX_BNKSEL_INT?)... unless Wayne could point out the right way to do that... hint hint.

Time to warm up the soldering iron.

Robb

[Ed Silky]

I'm currently working on a Z80 main board (full system) that uses a ST7C256 for the page register, providing 8 x 8K pages (that is a cache ram used in various systems). The board has 512K of ram and 512K of flash (1M on board) but provides 20 address lines (2M) and fully decodes 24 address lines (with the main-board memory being the 1st 1 meg). It is using the RC80/BP80 bus with fully buffered signals on the bus and supports a bus master (direction is correctly controlled for ZCTRL<=>BCTRL, ZDATA<=>BDATA, and Z+PgADDR<=>BADDR for memory, I/O, and mode-2 interrupts). The board is designed for up to a 12MHz clock without wait-states. It includes 1 80-pin bus connector, so an additional RAM/ROM board can easily be used in the bus. At reset (anytime paging isn't enabled) the main memory can be jumpered for; all-rom, all-ram, or 50/50 (ROM low 32K, RAM high 32K).

The board has a CTC and SIO on board. It brings the SIO-A serial out to a USB adapter and the SIO-B to a module for a USB keyboard. The module also provides an SD Card interface. I intend to implement an IDE interface for the SD Card. It also has a connector for an ERMC240128-2 240x128 OLED display or a 320x480 TFT display (Arduino module). 

The RC80/BP80 bus is also brought to 2 40-pin ribbon cable connectors. I plan to make a backplane with a few RC80/BP80 connectors on it that can connect to the main board via short ribbon cables, allowing it to be placed in-line (flat) or upright. Depending on which is better for an enclosure.

I'm at the stage of laying the board out. The board is 6.5" x 8.5".

I will be working on modifying the BIOS to support the 8x8K paging, so I'll keep people updated as I make progress. At the point that I have boards I'll start a topic to show its progress.

I designed Z80-based systems/peripherals in the early '80s and I'm working on it with another engineer that I worked with (who designed systems in the '70s-'90s).

-Ed

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[Wayne Warthen]

On Tuesday, October 21, 2025 at 6:02:07 AM UTC-7 Robb Bates wrote:

Digging more into  Dr Scott Bakers' ROM/RAM Module and  Sergey Kiselevs' Zeta 2 boards, it looks like that's exactly what it's designed to do.  Well, they look like they're trying to add two more RAM chips, but I think I'd prefer to add more ROM to grow the ROM disk capacity.  I think that just means some tweaking in the BIOS code to assign the right banks.

I'll have to wrap my head around that part of the code (HBX_BNKSEL_INT?)... unless Wayne could point out the right way to do that... hint hint.

Definitely not a problem for RomWBW.  I don't know offhand if the HBX_BNKSEL routine would need an update, but should be trivial if so.

-Wayne 

[Wayne Warthen]

Took a quick look at the Zeta 2 bank selection routine and it looks like it should handle increased ROM size as is.  Obviously, ROMSIZE will need to be adjusted.

Thanks, Wayne 

[Robb Bates]

But I'm thinking the '139 needs to be rewired so that Q0 and Q1 are on the two ROM chips and Q2 and Q3 are on the two RAM chips.  Or Q0, Q1 and Q2 are ROM (if using 3 ROM and 1 RAM chip) and Q4 on RAM.  I'm considering doing that latter as I'd prefer to have 1.5Mb of ROM disk and leave the RAM at its current size.  A bigger RAM disk isn't terribly useful... for me at least.

I need to walk through the circuit to make sure.

[Robb Bates]

If I were to just add on a second ROM chip and modify the ROMSIZE, but don't add any additional files to the ROM disk, do I need to flash the chip with anything before installing or will it just format the available space when I write enough new files to it in CP/M?  FYI, I'm using the MDFFENABLE feature.

Robb

[Mark T]

A ram disk can be more usefull if it has battery backup.

[Robb Bates]

It certainly can be.  I won't argue that.  But it wouldn't be much different than a CF drive in my particular setup.  Besides, I really like the fact that it's volatile.  I use it as a temp install directory to test out new programs.  If I don't like them, just cycle power and viola! Fresh clean empty drive.

[Wayne Warthen]

On Tuesday, October 21, 2025 at 12:12:49 PM UTC-7 Robb Bates wrote:

If I were to just add on a second ROM chip and modify the ROMSIZE, but don't add any additional files to the ROM disk, do I need to flash the chip with anything before installing or will it just format the available space when I write enough new files to it in CP/M?  FYI, I'm using the MDFFENABLE feature.

RomWBW will produce a ".rom" file that matches the size of the ROM of your system.  It doesn't know (or care) how many chips are involved.  Ideally, you would flash all of the required chips as appropriate for the full ROM image (breaking up the image as needed).  However, if you are not exceeding the capacity of the first ROM chip initially, then you can get away with just programming the first chip.

I think (but not sure) that MDFF understands 2 ROM chips.  I have no idea what it would do with 3 or more.  MDFF is rarely utilized and not well tested -- especially with more than one chip.

Thanks, Wayne

[Wayne Warthen]

Argh, Google Groups is dumping my posts again.  Trying again.

I wanted to add that the RomWBW build assumes the ROM space will be 0, 128K, 256K, 512K, or 1M.  If otherwise, you will need to tweak some parts of the build.  Take a look at Source/RomDsk/ReadMe.txt.

Thanks, Wayne

[Robb Bates]

Ah, good to know.  I'll just stick with 1M ROM and probably 512K RAM.  I assume it can do that without trouble.

Robb

[Wayne Warthen]

On Tuesday, October 21, 2025 at 1:20:44 PM UTC-7 Robb Bates wrote:

Ah, good to know.  I'll just stick with 1M ROM and probably 512K RAM.  I assume it can do that without trouble.

No problem.  There are other platforms with that exact configuration.