ARM32 binaries for CS, or building on ARM 32

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Joey Eremondi

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Aug 11, 2020, 1:58:03 PM8/11/20
to Racket Users
I'm wondering, does anybody have any prebuilt  32-but ARM binaries for Racket on Chez? I'm trying to run a little web-server on a raspberry pi, and I'd prefer to use the Chez version, but I can't seem to get it to build.

Alternately, if anybody knows why it won't build and can help, that would help. With eiether --enable-csracket or --enable-csonly, it gets stuck compiling the forked version of ChezScheme. Surprisingly, it doesn't seem to be an out of memory error. Is the illegal instruction error because it's ARMv6 and not AArch32?

...
gcc  
-Wpointer-arith -Wextra -Werror -Wno-implicit-fallthrough -O2 -g -O2 -Wall -DELF_FIND_BOOT_SECTION -pthread -rdynamic -o ../bin/tarm32le/scheme ../boot/tarm32le/main.o ../boot/tarm32le/libkernel.a -lm -ldl  -lpthread -lrt -luuid ../zlib/libz.a ../lz4/lib/liblz4.a -pthread
(cd s && make bootstrap)
make allx
rm
-f *.tarm32le xpatch patch *.patch *.so *.covin *.asm script.all header.tmp *.html
rm
-rf nanopass
cp
-p -f ../boot/tarm32le/petite.boot ../boot/tarm32le/sbb
cp
-p -f ../boot/tarm32le/scheme.boot ../boot/tarm32le/scb
make all
echo
'(reset-handler abort)'\
             
'(base-exception-handler (lambda (c) (fresh-line) (display-condition c) (newline) (reset)))'\
             
'(keyboard-interrupt-handler (lambda () (display "interrupted---aborting\n") (reset)))'\
             
'(optimize-level 3)'\
             
'(debug-level 0)'\
             
'(commonization-level (commonization-level))'\
             
'(compile-compressed #t)'\
             
'(compress-format (compress-format))'\
             
'(compress-level (compress-level))'\
             
'(generate-inspector-information #f)'\
             
'(subset-mode (quote system))'\
             
'(compile-file "cmacros.ss" "cmacros.so")'\
             
| ../bin/tarm32le/scheme -q
Error: illegal instruction
()
make
[10]: *** [Mf-base:375: cmacros.so] Error 1
make
[9]: *** [Mf-base:179: allx] Error 2
make
[8]: *** [Mf-base:196: bootstrap] Error 2
make
[7]: *** [Makefile:22: build] Error 2
make
[6]: *** [Makefile:20: build] Error 2
make
[6]: Leaving directory '/home/pi/gh/racket-7.8/src/ChezScheme'
make
[5]: *** [Makefile:158: scheme-make-finish] Error 2
make
[5]: Leaving directory '/home/pi/gh/racket-7.8/src/cs/c'
make
[4]: *** [Makefile:148: scheme-make-copy] Error 2
make
[4]: Leaving directory '/home/pi/gh/racket-7.8/src/cs/c'
make
[3]: *** [Makefile:137: scheme] Error 2
make
[3]: Leaving directory '/home/pi/gh/racket-7.8/src/cs/c'
make
[2]: *** [Makefile:60: cs] Error 2
make
[2]: Leaving directory '/home/pi/gh/racket-7.8/src/cs/c'
make
[1]: *** [Makefile:90: racketcs] Error 2
make
[1]: Leaving directory '/home/pi/gh/racket-7.8/src'
make
: *** [Makefile:53: all] Error 2


Matthew Flatt

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Aug 11, 2020, 5:14:28 PM8/11/20
to Joey Eremondi, Racket Users
Which model Pi are you using? I'm able to build on a Pi 3, so I wonder
if it's a difference in processors, where the Arm32 backend is using
something that it shouldn't.

Whether or not that guess is right, can you try running `gdb` in the "ChezScheme" directory like this?

env SCHEMEHEAPDIRS=tarm32le/boot/tarm32le/ \
gdb tarm32le/bin/tarm32le/scheme

Disassembling around the failed instruction address (with `disassemble`
in gdb) should clarify what instruction is misused.

Thanks,
Matthew
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Joey Eremondi

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Aug 11, 2020, 5:35:50 PM8/11/20
to Racket Users
I'm on an old RPi B (maybe a B+). It's pretty ancient, so I might be pushing my luck. Here's my CPU info:

pi@raspberrypi:~ $ cat /proc/cpuinfo
processor    
: 0
model name    
: ARMv6-compatible processor rev 7 (v6l)
BogoMIPS    : 697.95
Features    : half thumb fastmult vfp edsp java tls
CPU implementer    
: 0x41
CPU architecture
: 7
CPU variant    
: 0x0
CPU part    
: 0xb76
CPU revision    
: 7

Hardware    : BCM2835
Revision    : 000e
Serial        : 00000000e9b1ce2d
Model        : Raspberry Pi Model B Rev 2

Running GDB gives the illegal instruction as
<UNDEFINED> instruction: 0xf57ff05a
which looks to be a "Data Memory Barrier" instruction? Sounds like a plausible culprit.

Thanks!

Matthew Flatt

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Aug 11, 2020, 6:02:54 PM8/11/20
to Joey Eremondi, Racket Users
Ah, that makes sense.

Does configuring with `--enable-mach=arm32le` work?

Using "arm32le" instead of the inferred "tarm32le" avoids memory-fence
instructions, so it should solve this problem, but I'm not certain the
rest of the build will adapt correctly.
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joey.e...@gmail.com

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Aug 18, 2020, 10:36:29 AM8/18/20
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Alright, after compiling for approximately 16 hours, it looks like this works. Thanks so much!

Matthew Flatt

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Aug 24, 2020, 6:36:38 PM8/24/20
to joey.e...@gmail.com, Racket Users
I've fixed the memory fence on 32-bit Arm for the next release to use
an instruction that works on ARMv6, so you won't need to use
`--enable-mach=arm32le` in the future.

Also, the Utah snapshot site now provides ARMv6 builds for Racket CS:

https://www.cs.utah.edu/plt/snapshots/

Unfortunately, DrRacket CS uses enough additional memory (maybe in part
because places are enabled) that it fails soon after startup on my old
Pi B. So, just in case its useful to someone, the ARMv6 BC builds will
return in the next snapshot build.
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