Verilog verification in pymtl - general questions

54 views
Skip to first unread message

Damian Rypel

unread,
Apr 27, 2023, 8:59:12 AM4/27/23
to pymtl-users
I'm exploring what market has to offer in terms of verilog RTL verification in Python, and I came across pymtl, so I have couple questions:
1) pymtl is working only with Verilator simulator? Or i can be used with other commercial simulators (questa, vcs, xcelium, etc)?
2) pymtl can work with DUT in verilog/system verilog, but vhdl is not supported?
3) In one article I saw pyh2 library/framework, do you know if this is included in pymtl, or this is something separate?
4) Can you suggest some reference/training materials for developing pymtl testbench with verilog DUT?

Best regards,
Damian

Christopher Batten

unread,
Apr 28, 2023, 8:01:03 AM4/28/23
to Damian Rypel, pymtl-users
Hi Damian,

I'm exploring what market has to offer in terms of verilog RTL verification in Python, and I came across pymtl,

Thanks for your interest!

so I have couple questions:
1) pymtl is working only with Verilator simulator? Or i can be used with other commercial simulators (questa, vcs, xcelium, etc)?

Correct. PyMTL3's Verilog/SystemVerilog integration is currently only through Verilator.

2) pymtl can work with DUT in verilog/system verilog, but vhdl is not supported?

Correct.

3) In one article I saw pyh2 library/framework, do you know if this is included in pymtl, or this is something separate?

Yep ... to some degree the PyH2 paper is exploring how to combine PyMTL3 with the awesome Hypothesis library:


We have some Hypothesis strategies here:


But basically you can use all of the power of Hypothesis with PyMTL3 out of the box. In the paper, we discuss three example frameworks using the PyH2 approach. The first is for testing on-chip networks. You can see that here:


You can see examples of using Hypothesis to test various on-chip network components throughout that repo:


The second example framework was for processors and to be honest I am not sure we every polished up that code and made it public. It was a tad hacky since it required gluing PyMTL3 together with PicoRV32. But I think the paper made a strong case for this general approach and indeed there has been follow up work by the University of Cambridge that pushes this idea even further:


The third example framework uses Hypothesis's state-based property-based random testing by leveraging PyMTL3's unique unified modular ordering constraints. We have a great paper at DAC on this technique:


I am not sure if the actual reorder buffer every made it into a public GitHub repo, but I can check.

4) Can you suggest some reference/training materials for developing pymtl testbench with verilog DUT?

Sure. We have had 100+ students this year using PyMTL3 with Verilog DUTs. You can go through this tutorial:


Just be aware you need to install the ece4750-2022 branch for the above tutorial to work. You can easily install that branch with pip in a virtual environment like this:

 % mkdir $HOME/pymtl3-demo
 % cd $HOME/pymtl3-demo
 % python3 -m venv pymtl3
 % source pymtl3/bin/activate

Feel free to post any follow up questions here!
Chris

--
You received this message because you are subscribed to the Google Groups "pymtl-users" group.
To unsubscribe from this group and stop receiving emails from it, send an email to pymtl-users...@googlegroups.com.
To view this discussion on the web visit https://groups.google.com/d/msgid/pymtl-users/9cb74533-0eed-4992-ba82-85dc6a65b8edn%40googlegroups.com.

Damian Rypel

unread,
May 4, 2023, 3:52:31 PM5/4/23
to pymtl-users
But you don't have any "classic" documentation e.g. with explanations what framework functions do?

For example, if I want to simulate something there are:
sim_reset() -> I guess this function resets DUT. So DUT must have reset signal with name reset? How long this reset takes?
sim_tick() -> this is one clock tick? So simulation progress for one clock posedge? What if I want to  use negedge?
And maybe one more question - what about concurrent tasks? Pymtl have something like fork join or several initial blocks like in verilog? Or there is no parallelism? 

I'm trying to find some answers, but I don't see any documentation, so right now it looks like I can only ask here or dig into the code, so basicaly reverse engineering - not very efficient way;)

Best regards,
Damian

Christopher Batten

unread,
May 5, 2023, 9:30:56 AM5/5/23
to Damian Rypel, pymtl-users
Hi Damian,

But you don't have any "classic" documentation e.g. with explanations what framework functions do?

Correct. PyMTL3 is still very much a work in progress!

For example, if I want to simulate something there are:
sim_reset() -> I guess this function resets DUT. So DUT must have reset signal with name reset? How long this reset takes?

Right ... sim_reset is just a convenience function which sets reset high for three cycles:


sim_tick() -> this is one clock tick? So simulation progress for one clock posedge?

Correct ... sim_tick advances to the next cycle.

What if I want to  use negedge?

PyMTL3 currently only supports positive edge triggered sequential blocks.

And maybe one more question - what about concurrent tasks? Pymtl have something like fork join or several initial blocks like in verilog? Or there is no parallelism? 

PyMTL3 does not support fork/join nor does it support initial blocks although you can just set signals from top before the simulation starts. Keep in mind that fundamentally PyMTL3 is not support an arbitrary discrete event timing model ... it supports a cycle-level timing model. WE do make use of the Python greenlet library for some of our more advanced adapters and such which enables you to basically yield in the middle of a concurrent block until the next cycle. There are many, many things you can model in Verilog that you cannot model in PyMTL3.

I'm trying to find some answers, but I don't see any documentation, so right now it looks like I can only ask here or dig into the code, so basicaly reverse engineering - not very efficient way;)

Yep ... it is what it is though. If you really want to learn about what PyMTL3 can and cannot do I just recommend going through the tutorial I mentioned below:


We have had many, many students learn PyMTL3 to be productive digital RTL designers by just going through this tutorial ... you might also want to go through this tutorial if you want learn more about PyMTL3's concurrent blocks and such:


If you go through those tutorials you will really understand what the framework's capabilities are.

If you are looking for a library that is super polished with tons of documentation then PyMTL3 might not be the right choice. But if you are looking for a neat library for hardware modeling that takes a different approach from many other frameworks and you are willing to dive into the implementation details it might be a fun library to explore!

We are of course happy to provide help via this mailing list ...

There are many other cool Python-based design verification frameworks to like MyHDL, Migen, CocoTB, etc.

Best,
Chris

Reply all
Reply to author
Forward
0 new messages