pymtl3 still active supported?

70 views
Skip to first unread message

David Peng

unread,
Apr 19, 2023, 5:46:48 AM4/19/23
to pymtl-users
Hi, sir/madam,

I am searching for python-based rtl design tool and found pymtl3.

Is this project still active? Where do I get general support? Last message on this group was August last year.

It seems the https://pymtl3.readthedocs.io/en/latest/ is very limited. Where should I start?

Thanks,
David

Christopher Batten

unread,
Apr 19, 2023, 3:42:28 PM4/19/23
to David Peng, pymtl-users
Hi David,

PyMTL3 is definitely still active although most of the users are all at Cornell currently. We had over 100 students use PyMTL3 this past year in both our senior-level computer architecture course and our graduate course in chip design, although in the interest of full disclosure those students were doing their RTL design in Verilog and then using PyMTL3 for testing, functional models, simulation harnesses, etc.

Although I agree our documentation is still limited ... improving documentation is on our list for the upcoming year!

To get started, try this:

### setting up virtual environment

 % mkdir $HOME/pymtl3-demo
 % cd $HOME/pymtl3-demo
 % python3 -m venv pymtl3
 % source pymtl3/bin/activate
 % pip install pymtl3
 % pip install ipython
 % ipython

### bits

 >>> from pymtl3 import *
 >>> a = Bits8(6)
 >>> a
 >>> b = Bits8(3)
 >>> b
 >>> a | b
 >>> a << 4
 >>> c = (a << 4) | b
 >>> c
 >>> c[4:8]

### full adder

 >>> from pymtl3.examples.ex00_quickstart import FullAdder
 >>> import inspect
 >>> print(inspect.getsource(FullAdder))

 >>> fa = FullAdder()
 >>> fa.elaborate()
 >>> fa.apply( DefaultPassGroup() )
 >>> fa.a   @= 0
 >>> fa.b   @= 1
 >>> fa.cin @= 0
 >>> fa.sim_eval_combinational()
 >>> fa.sum
 >>> fa.cout

 >>> fa = FullAdder()
 >>> fa.apply( DefaultPassGroup(textwave=True) )
 >>> fa.sim_reset()
 >>> fa.a   @= 0
 >>> fa.b   @= 1
 >>> fa.cin @= 0
 >>> fa.sim_tick()
 >>> fa.a   @= 1
 >>> fa.b   @= 0
 >>> fa.cin @= 1
 >>> fa.sim_tick()
 >>> fa.print_textwave()

### translation

 >>> from pymtl3.passes.backends.verilog import *
 >>> fa = FullAdder()
 >>> fa.set_metadata( VerilogTranslationPass.enable, True )
 >>> fa.apply( VerilogTranslationPass() )
 >>> exit
 % more FullAdder_noparam__pickled.v

If you want to use Verilog for your RTL design and then use PyMTL3 for testing, FL modeling, etc I recommend doing this tutorial:


You will need to use the ece4750-2022 branch of PyMTL3 though. You can easily install that branch with pip in a virtual environment like this:


If you want house PyMTL3 for RTL design then you might want to try this tutorial:


I think that tutorial will work fine with the master branch of the PyMTL3 repo. Feel free to post and questions to this list!

Best,
Chris

--
You received this message because you are subscribed to the Google Groups "pymtl-users" group.
To unsubscribe from this group and stop receiving emails from it, send an email to pymtl-users...@googlegroups.com.
To view this discussion on the web visit https://groups.google.com/d/msgid/pymtl-users/6a0d6f4e-7a3f-4c82-b9bd-80ceae2bf3a9n%40googlegroups.com.

Reply all
Reply to author
Forward
0 new messages