weird error on @= assign to list of InPort

[David Peng]

Hi,

I encountered below error in writing test for SortUnitFL.

test/sortfl_test.py:23: in t
    model.sim_tick()
../../Library/Python/3.9/lib/python/site-packages/pymtl3/passes/sim/SimpleTickPass.py:28: in iterative
    blk()
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

    def check_top_level_inports():
      assert s.reset is obj0, 'Please use @= to assign top level InPort top.reset'
>     assert s.in_[1] is obj1, 'Please use @= to assign top level InPort top.in_[1]'
E     AssertionError: Please use @= to assign top level InPort top.in_[1]

Here is my code:

def test_basic():

model = SortUnitFL()

model.apply(DefaultPassGroup(linetrace=True))

model.sim_reset()

def t(in_, out):

model.in_val @= 0x1

for i, in_v in enumerate(in_):

model.in_[i] @= in_v

model.sim_eval_combinational()

if out != '?':

for i, out_ in enumerate(out):

assert model.out[i] == out_

model.sim_tick()

t([1, 3, 3, 4], '?')

t([5, 3, 3, 4], [1, 3, 3, 4])

#this will not generate any error

#t([2, 3, 3, 4], [0x1, 0x3, 0x3, 0x4])

As you see in comment, if I change the number '5' to '2', it can pass without any issue.

Thanks,

David

[Peitian Pan]

Hi David,

Can you try wrapping the integers in your test vectors with the BitsN data types in PyMTL3? Assuming your input/output ports are of 32-bit wide you can do the following

t([b32(1), b32(3), b32(3), b32(4)], '?')

where b32 is simply the abbreviation of Bits32.

Best,

Peitian

[David Peng]

Hi, Peitian,

My width is 8 (as default). So I tried with b8, but the error is the same. The error is on the second line: "t([5, 3, 3, 4], [1, 3, 3, 4])", not on the first line.

I changed my python to 3.7.16, the error is the same. 

I even tried the file  https://github.com/cornell-ece5745/ece5745-tut3-pymtl/blob/master/sim/tut3_pymtl/sort/test/SortUnitFL_test.py with python 3.9.6. The error is the same.

Are you able to reproduce the issue with my simple test?

Thanks,

David

[David Peng]

The error is a little bit different, now it even report assignment to in_val as error:

      t([b8(1), b8(3), b8(3), b8(4)], '?')
>     t([b8(4), b8(3), b8(3), b8(4)], [1, 3, 3, 4])

    def check_top_level_inports():
      assert s.in_val is obj0, 'Please use @= to assign top level InPort top.in_val'
      assert s.reset is obj1, 'Please use @= to assign top level InPort top.reset'
>     assert s.in_[2] is obj2, 'Please use @= to assign top level InPort top.in_[2]'
E     AssertionError: Please use @= to assign top level InPort top.in_[2]

[Yanghui Ou]

Hi David,

I tried your code and the test passed on my end. I could not reproduce the error you are seeing no matter how I change the input vector. Could you send us step by step command on how we can reproduce your error (preferably starting from how you install pymtl3)? I have attached the code that I ran. Should be the same code as yours?

Best,

Yanghui

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[Christopher Batten]

Thanks Yanghui and Peitian!

David, please also feel free to create a GitHub repo with some code to make it easier for us to try and reproduce any issues and help.

Best,

-c

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<example.py>

[David Peng]

Yanghui/Peitian,

Thanks for your help.

My system is Mac OS, with python version 3.7.16. I just use pip to install pymtl3. Should I use GitHub to clone your latest master branch instead?

I'll try to upload to a GitHub repo later.

Thanks,

David 

[David Peng]

Hi, Yanghui/Peitian,

I figured out the error and the fix.

In my sort_fl, I didn't copy the input argument arr, but manipulate the arr directly and return the same arr(!). This is a bad coding style. After I make a copy and return the copy, the issue is gone.

The buggy code seems swap SortUnitFL.in_ InPort, but I have no idea why it will generate such error in certain input value but not others.

Thanks,

David

[David Peng]

BTW, any requirement of python version? I saw other thread of staying with 3.7, is it still the case?

Thanks,

David

[Christopher Batten]

Glad you figured it out! Yes, the way Python always treats objects as references can take a little getting used to ...

I think Shunning Jiang updated PyMTL3 so it should work with newer versions of Python ... but let us know if you see any issues or have any other questions!

Best,

Chris

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[David Peng]

Another question: I saw the limit of 1024bit of Bits class. What if I want to expand to 4096 or even 8192?

I am looking for a system-level simulator with RTL capability for network device.For modern device's high bandwidth, the limit of 1024b is too small.

Thanks,

David

[Christopher Batten]

I think it depends on what you are trying to model? An 8192 bit vector is quite large? If you are trying to model network packets, then usually int hardware we do not handle an 9Kb packet all at once but instead work on it in smaller chunks ... note you can definitely model larger memories and such just like in Verilog. You just need an array of wires ... I imagine you could also hack PyMTL3 to remove the check on bit width ... not sure the implication on simulation performance though.

-c

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[David Peng]

Hi, Dear Christ,

Regarding performance, do you have any public data on it? Python simulation vs industrial or academic verilog simulator (e.g. verilator).

Thanks,

David Peng

[Christopher Batten]

You could check out this paper:

https://www.csl.cornell.edu/~cbatten/pdfs/jiang-mamba-dac2018.pdf

If you are just using Python it will be very slow, but then again if you are writing pure RTL models you can always use PyMTL3 to translate to Verilog, compile into a C++ shared library using Verilator, and then wrap everything back up in Python automatically ... then the performance will be more like Verilator.

If you are modeling smaller blocks of hardware then you probably won't notice. If you are trying to model a very large complex SoC in PyMTL3 then simulation performance will start to be more of an issue.

Best,

Chris