PDP-1 hardware

[Bill E]

After digging thru the engineering docs for the PDP-1, it has some pretty strange tech.

I wonder just how the designers came up with it? I imagine the TX-0 used the same.

Rather than doing what we would think of as digital circuitry, it's really an AC-coupled semi-analog beast using pulse transformers, capacitor-coupled gates, and bunches of pulse amplifiers. Interesting logic voltage levels, too. As in, -3 volts for logical 1.

Anyone have any history or ideas?

[Glenn Babecki]

Here's a Google (AI?) summary of the pulse logic rationale, which is more extensive than I could come up with off the top of my head.

https://www.google.com/search?client=firefox-b-1-m&q=why%20where%20pulse%20transformers%20used%20in%20early%20digital%20logic

I believe the negative logic voltage paradigm was primarily the result of most early transistors being the PNP type.  However there may have been other subtle reasons.  TTL style logic with NPN transistors that supported positive logic level voltages didn't become commercially available until about 1964 or 1966 if you count the 74 series gates.

My 2¢ but there is probably more rationale out there somewhere.

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[Matthias Barthel]

Very interesting, i have a few pdf's here from bitsavers with the schematics of the logicmodules from the pdp1, eventually helps the AI me to understand the modules

Matthias 

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[Glenn Babecki]

Oh, and I believe all the transformer-capacitor pulse logic was also responsible for all the whacky voltage supplies you see in those circuits.  I've avoided studying these circuits in detail because they hurt my head, and I'd never want to recreate them in real life. 😉

[Matthias Barthel]

😂😂

I'd like to have some modules here, just nice to have 😉 

But maybe we can build 🙃 the modules in cmos and create a cmos-pdp1 😁

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[Bradford Miller]

“Better” ;-) : ECL (or LVPECL). Not only could we replicate some of the original power hogging (you’ll NEED fans), but also have a much faster PDP-1! Plus we could build our own KL10 using similar flip chips!

[Bill E]

I remember as a kid when I was still building stuff with vacuum tubes, then some early transistors. When ICs started becoming available, I thought that was the end of electrical engineering, no one would have to design anything anymore, just hook up little blocks. :)

[Glenn Babecki]

I was right there with you, re tubes to early transistors.

The advent of ICs didn't really spell the end of "electrical engineering." There was/is still plenty of engineering in higher speed circuit design and layout.  However, I'm beginning to believe that AI will spell the end of EE as we knew it.  I believe you're an MIT alumni but I don't recall your course.  If you've caught wind of the planned changes in Course 6 (EE) you'll see they are all focused on CS and AI related stuff, and seemingly all bit abandoning "traditional" EE training.  There was quite the flap on campus and the alumni community, but time matches on...sigh. ☹️

On Wed, Oct 15, 2025, 1:54 PM Bill E <wjegr...@gmail.com> wrote:

I remember as a kid when I was still building stuff with vacuum tubes, then some early transistors. When ICs started becoming available, I thought that was the end of electrical engineering, no one would have to design anything anymore, just hook up little blocks. :)

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[Bill E]

Yes, course 6. I've been thinking the curriculum there has been going downhill for a while. I was the last year before they split 6 into 6.1 and 6.3, in the first AI glory days. (not) Hence my PDP-1, -10, etc. interest.

Bill

[Milo Velimirović]

I would work backwards from the architecture level to implement in CMOS or whatever your favorite logic family is. Or go the FPGA route. Almost any small development board ought to have enough logic elements and I/O pins to accommodate a PDP-1. Another challenge would be the interface glue circuitry to drive a PiDP-1 console and devices.

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[Glenn Babecki]

Yes there are a lot of ways to "skin that cat" ( probably not the best phrase anymore), but I think Matthias was fantasizing about going "old school" and keep to the original logic implementation - there be dragons there.  The pulse transformer parts are potentially challenging.  It can either be considered seriously tricky engineering or black magic as witnessed by the tweaking that often occurred in those designs to keep things synchronous...or not as the designed called for.

If I'm not mistaken, Angelo experimented with the initial PDP-1 implementation in VHDL or Verilog.

[Glenn Babecki]

Bill,

I think the euphemistic explanation we got for the curriculum change is it "evolved" to keep up with the times.  Us previous generation EEs sarcastically, rhetorically asked "Well who is going to build your AI equipment and provide the power for the data centers?" 🤔

[Michael J. Kupec]

keep to the original logic implementation - there be dragons there.  The pulse transformer parts are potentially challenging. 

Pulse transformers - started bringing back old memories of walking into flight simulator shops based on AC theory hardware and the familiar smell of roasting shellac and transformer paper! 

Most notably the old B-52 sim at Seymor Johnson AFB! 😂

(Damn I’m old!)

Have a great Day!

Michael J Kupec 

Sent from my iPhone

On Oct 15, 2025, at 3:38 PM, Glenn Babecki <glenn....@gmail.com> wrote:



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[Matthias Barthel]

Yes, Glenn, your'e right! i love the old school electronics  :) a FPGA PDP1 already exists (https://github.com/hrvach/fpg1)

Matthias

[Glenn Babecki]

Matthias,

Yes I came across Hrvoje Čavrak's PDP-1 FPGA implementation, I think before I noted Angelo's work.  Angelo had a variety of reasons for not using his own early FPGA design or a SIMH approach to the PiDP-1 we have today.  I never looked into Hrvoje's implementation to note if he had issues with any of the available PDP-1 software.

I'm most likely going to stick with the current PiDP-1 implementation growing pains, if for no other reason than to ride the wave of getting the legacy tools and software working.  In addition, I have a number of other electronic projects that I need to focus on.

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[Bill E]

Angelo did a great job at replicating the actual timing of the hardware, down to the length of each subclock duration. I'm not sure how accurate simh or the fpga implementations are about the overall 5us/10us instruction cycle time, and as far as I know, simh doesn't try to replicate any of the subclocks. Does it matter? Well, the instruction cycle time does, maybe the subclocks aren't critical, but it's still excellent. BTW, the -1 has 11 subclock periods within an instruction cycle, of varying lengths. According to the manuals, those were done with delay lines. (!)

Angelo implements his simulation such that each operation within a cycle happens when it did on the real -1.

BTW, that was a help/hinderance while implementing the dynamic IOTS to handle the wait/nowait continue/nocontinue logic. I had to resort to the hardware description and work up a state diagram. Various bits have to be done during the correct subcycle to work. But from what I can tell, it works exactly like the hardware did.

Bill

[Glenn Babecki]

Bill,

I remember Angelo saying his main focus was getting the cycle times accurate.  As you indicate, clearly that's not the forte of SIMH.  I suspect that while doable in an FPGA, it would have been a lot of work.  Ha, you gotta love delay lines.  They are indeed sprinkled around the PDP-1 circuitry.

Hats off to you and Angelo for persevering on faithfully replicating the cycle timing.  I wish I had time to muck around with that sort of stuff...rather than the pulse logic bits of the design.  These changes are coming fast and furious such that it seems all I can do is keep up with the emails. 😁

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[Norbert Landsteiner]

Regarding the general architecture, mind that a considerable amount of modules predate the PDP-1.

Before the PDP-1, DEC was exclusively in the business of designing digital modules for lab purposes and the PDP-1 was meant to be constructed from those. It didn't just work out like that and the PDP-1 incorporated also custom designed modules, but this is also how it was possible to design the computer in just three and a half months.

Regarding timing, I think most existing emulators will get the timing right at memory cycle granularity (5 µs). Which is what mostly matters externally. The notable exception here is the automatic hardware multiply/divide, which inserts a timing chain of its own and will complete in variable time. (MUL will complete in about 14-25 µs and DIV in about 30-40 µs. Usually, emulators will use the respective average, which roughly coincides with the average execution time stated by DEC.)

Internal timing is important for in what order micro-programmable instruction will execute. (E.g., CLA will execute before CMA, so we can load -1 into AC by "cla+cma-opr".) But this may be simulated rather easily just by the order of conditions in emulation code, as the total execution time will be again 5µs.

While this should be good enough for basic emulation, like running visual code, there are probably much more complex interactions with various devices (e.g. magnetic tape and DMA, magnetic drum, etc.), which afford a much more subtle approach. I think, no emulator has gone there before and this is a really ground-breaking feature of Angelo's emulator.

A general observation::

I think, the role of the development and availability of power supplies and oscilloscopes (inspectability of voltage vs. time) is generally underrated. Oscilloscopes became only available in the early 1930s and the required power supplies became really feasible only after this. And, as these prerequisites fell into place, it didn't take long for computers or computer-like appliances to pop up. (E.g., Tommy Flowers began his experiments with tubes [brit.: valve] for switching in 1934 and had built a tube-based memory prototype for the British Post Office just before the war.)

Power supplies were a particular concern. There was a limited awareness in the 1950s that ternary logic may be more efficient (e.g., Wiener had discussed this in the late 1940s; compare also the report of the Engineering Research Associates Staff on High Speed Computing Devices, 1950), but I kind of doubt that this would have been feasible with the limitations of the power supply technology of the time, especially with large-scale tube computers. (Notably, the famous SETUN was solid state using ferrite cores for switching, which may be more than a coincidence.)

Best,

Norbert

[Glenn Babecki]

I guess it was sort of like this back in the day. 🤭

https://m.youtube.com/watch?v=F226oWBHvvI

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[Alen Shapiro]

Indeed!

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[Whit Turner]

I worked for DEC as a support engineer starting in 1976. By that time, DEC was selling mostly TTL-based PDP11s and that is what I was familiar with. Many of the older systems had been retired by then. One day, I was asked to trouble shoot a customer's broken PDP9, something I had never seen. I arrived and grabbed the print set, which was filled with negative logic diagrams. After taking several deep breaths, I began to (slowly) understand the logic and eventually resolved what was a core memory issue, using my trusty Tektronix 465. Fortunately, that was my first and last encounter with the DEC negative logic designs!

Whit

[Glenn Babecki]

Whit,

Don't know where you live, but a visit to the Rhode Island Computer Museum will bring back (core) memories. They have one of the only operational PDP-9s, but I'm sure they could use help keeping it going. 😉  Assuming you won't get VietNam PTSD flashbacks, check out the extensive restoration blog on their website (https://www.ricomputermuseum.org/collections-gallery/equipment/dec-pdp-9/pdp-9-restoration).  I was there last May to tour and discuss some PDP-9 details for a throwback project and it was an impressive feat putting that back together.

Apparently the only other one somewhere in France was working until they moved it. Last I heard it wasn't fully operational, but that was some time ago and may be back online.

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[Whit Turner]

The RI Computer Museum is on my bucket list. I'm only a couple of hours away. 

The PDP-9 was actually a pretty cool machine (basically an improved PDP-7). From the console, you could select different clock speeds (including some VERY slow ones) and watch the data display as it stepped through a program. Or you could crank it all the way and see if something got flakey. All this is just a dim memory from my single encounter with a machine at Western Electric in 1977. It had an RD10 disk attached (another nightmare) and a TU-20 tape drive like the one at RI. I recall that the TU-20 was OEM'ed from HP and that it made horrible clanking noises when the tape started and stopped (due to the reel motor brakes).

Whit

[Glenn Babecki]

Look up Michael Thompson, he's the PDP-9 guru.  I'm sure you'll have lots of stories to swap.  He been my go-to guy to reconstruct (and relearn) a SIMH PDP-9 ADSS development environment. 👍

Unfortunately I'm stuck trying to sort out the display I used on the MIT lab computer back in the day.  I'm also trying to find source for the lab image processing library binary I have; much bigger challenge.

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[Haritech (Gmail)]

We ran a PDP-9 with 16k core and a 1M word drum in the laboratory. It ran MUMPS-9 and had 8 terminals and a 16 channel ADC. The terminals were used for data collection at the benches. The system took in work requests and generated work sheets for the techs to know what tests to run. At days end it generated reports back to the doctors. 

Been looking for a tape or listing of MUMPS-9. I think the last copy went with the machine when it was retired for a new PDP-11/70. 

Lawrence

On Oct 16, 2025, at 10:24, Glenn Babecki <glenn....@gmail.com> wrote:



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[Michael Thompson]

That PDP-9 with a disk could have run UNIX V0.

On Oct 16, 2025, at 5:10 PM, Haritech (Gmail) <lha...@haritech.com> wrote:



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[Haritech (Gmail)]

Yes though I didn’t know that at the time. We got the MUMPS system from Massachusetts General Hospital where I think they ran it on a PDP-15. Name stands for Massachusetts Utility Multi Programming System. It was self contained though I ran Monitor 9 after hours and played with Assembler (Macro 9?), Focal and Fortran. 

It was a great ‘little’ machine. 

Lawrence

On Oct 16, 2025, at 15:43, Michael Thompson <michael.9...@gmail.com> wrote:



[Lars Brinkhoff]

I'd like to have some modules here, just nice to have 😉 

But maybe we can build 🙃 the modules in cmos and create a cmos-pdp1 😁

With hundreds or thousands to build a computer, that's going to be expensive even if you manage to make a module at $10.

But for starters, how about simulating the modules in Verilog, VHDL, or C?  Then could build your virtual PDP as per the schematics.  Once that works, maybe go on to real hardware.

[Angelo Papenhoff/aap]

You can find my verilog PDP-1 here, though i never put it on an FPGA because peripherals are always a pain: https://github.com/aap/blincolnlights/tree/cfc879f69ef8bf7b90e748449432968bc585810d/pdp1_verilog

I had written the verilog code first because it's easier to transcribe schematics that way. Running it through verilator to generate a c++ simulation worked, but was way too slow. So I wrote a new emulator from scratch in C but still wanted to keep it as accurate as possible. Maybe the code should be a bit more visible than behind an old commit in the blincolnlights repo... unfortunately i'm super chaotic that way :/

Hrvach's FPGA PDP-1 is not at all based on the original schematics but is a completely independent implementation.

As for the logic: it is based on the TX-0 modules. The same basic principle was used in the later PDPs as well, only the PDP-6 introduced a kind of flying pulse rather than the memory-oriented approach with a fixed cycle. Even the KA10 still works that way and the KI10 sort of simulates it with flip-flops and a somewhat complicated clock network.