[PATCH] aarch64: implement feenableexcept/fedisableexcept/fegetexcept

[Waldemar Kozaczuk]

This patch adds real implementation of feenableexcept/fedisableexcept/fegetexcept.
The new code mostly comes from newlib (file newlib/libc/machine/aarch64/sys/fenv.h as of commit fd5e27d362e9e8582dd4c85e52c50742c518345d).

This new functionality is not enough to get tst-feexcept.cc
working because sigsetjmp/siglongjmp is still missing.

Signed-off-by: Waldemar Kozaczuk <jwkoz...@gmail.com>
---
arch/aarch64/feexcept.cc | 70 ++++++++++++++++++++++++++++++++++------
1 file changed, 61 insertions(+), 9 deletions(-)

diff --git a/arch/aarch64/feexcept.cc b/arch/aarch64/feexcept.cc
index 0d296314..9b0e9eec 100644
--- a/arch/aarch64/feexcept.cc
+++ b/arch/aarch64/feexcept.cc
@@ -5,31 +5,83 @@
* BSD license as described in the LICENSE file in the top-level directory.
*/

-#include <osv/types.h>
-#include <osv/stubbing.hh>
+/*-
+ * Copyright (c) 2004-2005 David Schultz <d...@FreeBSD.ORG>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#include <sys/types.h>
#include <fenv.h>
#include <__fenv.h>
// Note that musl's fenv.h does not define feenableexcept and friends, so
// we need to 'extern "C"' them here, as no header file does this.

+// Please note that most of the code below comes from newlib
+// (file newlib/libc/machine/aarch64/sys/fenv.h as of commit fd5e27d362e9e8582dd4c85e52c50742c518345d)
+// almost as-is except where it has been formatted to match this file.
+
+typedef __uint64_t _fenv_t;
+
+/* We need to be able to map status flag positions to mask flag positions */
+#define _FPUSW_SHIFT 8
+#define _ENABLE_MASK (FE_ALL_EXCEPT << _FPUSW_SHIFT)
+
+#define __mrs_fpcr(__r) __asm __volatile("mrs %0, fpcr" : "=r" (__r))
+#define __msr_fpcr(__r) __asm __volatile("msr fpcr, %0" : : "r" (__r))
+
+#define __mrs_fpsr(__r) __asm __volatile("mrs %0, fpsr" : "=r" (__r))
+#define __msr_fpsr(__r) __asm __volatile("msr fpsr, %0" : : "r" (__r))
+
extern "C"
int feenableexcept(int mask)
{
- WARN_STUBBED();
- // The feenableexcept says it returns -1 on failure.
- return -1;
+ _fenv_t __old_r, __new_r;
+
+ __mrs_fpcr(__old_r);
+ __new_r = __old_r | ((mask & FE_ALL_EXCEPT) << _FPUSW_SHIFT);
+ __msr_fpcr(__new_r);
+ return ((__old_r >> _FPUSW_SHIFT) & FE_ALL_EXCEPT);
}

extern "C"
int fedisableexcept(int mask)
{
- WARN_STUBBED();
- return -1;
+ _fenv_t __old_r, __new_r;
+
+ __mrs_fpcr(__old_r);
+ __new_r = __old_r & ~((mask & FE_ALL_EXCEPT) << _FPUSW_SHIFT);
+ __msr_fpcr(__new_r);
+ return ((__old_r >> _FPUSW_SHIFT) & FE_ALL_EXCEPT);
}

extern "C"
int fegetexcept()
{
- WARN_STUBBED();
- return -1;
+ _fenv_t __r;
+
+ __mrs_fpcr(__r);
+ return ((__r & _ENABLE_MASK) >> _FPUSW_SHIFT);
}
--
2.26.2

[Commit Bot]

From: Waldemar Kozaczuk <jwkoz...@gmail.com>
Committer: Nadav Har'El <n...@scylladb.com>
Branch: master

aarch64: implement feenableexcept/fedisableexcept/fegetexcept

This patch adds real implementation of feenableexcept/fedisableexcept/fegetexcept.
The new code mostly comes from newlib (file newlib/libc/machine/aarch64/sys/fenv.h as of commit fd5e27d362e9e8582dd4c85e52c50742c518345d).

This new functionality is not enough to get tst-feexcept.cc
working because sigsetjmp/siglongjmp is still missing.

Signed-off-by: Waldemar Kozaczuk <jwkoz...@gmail.com>

Message-Id: <20201007021918.32...@gmail.com>

---
diff --git a/arch/aarch64/feexcept.cc b/arch/aarch64/feexcept.cc