Hi,
I'm trying to simulate the bare metal multithreaded benchmarks that come with riscv-tests on a multicore Ariane OpenPiton setup using VCS. This includes mt-memcy, mt-vvadd, mt-matmul, and mm. I tried out both -march=rv64imafdc_zicsr and rv64imafdc_zicsr_zifence machine types when compiling the workloads as well. However, in both cases, the simulation fails with a bad trap.
50151500 : Simulation -> FAIL(HIT BAD TRAP)
Is there anything I'm doing wrong? I also tried adding thread count, thread stride, and finish mask as arguments based on the simulation manual.
sims -sys=manycore -vcs_run -x_tiles=2 -y_tiles=1 mt-memcpy.riscv -midas_args=-DTHREAD_COUNT=2 -midas_args=-DTHREAD_STRIDE=1 -precompiled -ariane -rtl_timeout 1000000
sims -sys=manycore -vcs_run -x_tiles=2 -y_tiles=1 mt-memcpy.riscv -midas_args=-DTHREAD_COUNT=2 -midas_args=-DTHREAD_STRIDE=2 -finish_mask=11 -precompiled -ariane -rtl_timeout 1000000
Thank you,
Yasas