Time taken for Gate Level Simulation

[Zaid Manzoor Khan]

Hello
I am currently trying to do Gate Level Simulation using manycore model. I created the model and replaced RTL references with my Netlist.
But it seems to be taking a very long time and is not moving ahead from this point. How much time can I expect it to take? Its already 24 hours.
I have also attached the simv log and this was the test that I am running on it - princeton-test-test.s and simulation model built is manycore.
sims -sys=manycore -x_tiles=1 -y_tiles=1 -vcs_run princeton-test-test.s


midas: bw_m4  --include=. --include=.. < diag.cpp > diag.m4
midas: Same args, same input, old products still exist.  My work here is done.
midas: ###########################################################
midas: ##  COPY PHASE
midas: ###########################################################
midas: rm -f ../diag.s ../mem.image ../diag.ev ../symbol.tbl ../diag.exe ../diag.pl
midas: Hard linking diag.s to '..'.
midas: Hard linking mem.image to '..'.
midas: Hard linking diag.ev to '..'.
midas: Hard linking symbol.tbl to '..'.
midas: Hard linking diag.exe to '..'.
midas: cd ..
midas: ###########################################################
midas: ##  CLEANUP PHASE
midas: ###########################################################
midas: Build directory already existed, so not removing it.
sims: locating diag default.dat
sims: Looking for diag under $DV_ROOT/verif/diag
sims: Found diag under /ece/home/khanx290/Desktop/OpenPiton/piton/verif/diag/efuse/default.dat
sims: /ece/home/khanx290/Desktop/OpenPiton/build/manycore/rel-0.1/simv +cpu_num=0 +dowarningfinish +doerrorfinish +spc_pipe=0 +vcs+dumpvarsoff +TIMEOUT=50000 +wait_cycle_to_kill=10 +tg_seed=0 +good_trap=0000082000:1000122000 +bad_trap=0000082020:1000122020 +efuse_data_file=efuse.img +asm_diag_name=princeton-test-test.s +efuse_image_name=default.dat +dv_root=/ece/home/khanx290/Desktop/OpenPiton/piton
sims: VCS_HOME is /apps/common/synopsys/vcs_2014.12
sims: setenv VERA_LIBDIR /ece/home/khanx290/Desktop/OpenPiton/build/manycore/rel-0.1/vera
sims: LM_LICENSE_FILE : /apps/common/synopsys/license/license.dat
sims: sim_start Sat Oct 29 14:54:04 CDT 2016
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version J-2014.12-SP2_Full64; Runtime version J-2014.12-SP2_Full64;  Oct 29 14:54 2016
Info: Core available value = ffffffff
Info->off_random_sys=0
Info(5315000): Qsel value(0)
Info(5315000):2 cpx request 1
(5316000)Info: cpx packet from iob ->1700000000000000000000000000000010001
Info(5316000):2 cpx request 0
IOB sending to tile X:  0 Y:  0
   raw tileid 00000000
Iob NOC2 sent a packet: 0000000000484000
Iob NOC2 sent a packet: 0000000000010001

Thanks
Zaid

[Yaosheng Fu]

Hi Zaid,

The problem is that you cannot use cross-module reference to monitor the internal signals any more in the gate-level simulation so none of those monitors that check internal states will output anything. Therefore there is no way to tell whether a test passes or not and it will just run forever. For gate-level simulations, we have another framework that adopted from OpenSPARC T1 which record all input and output signals of a VCS simulation and replay on a gate-level simulation to see whether it has the same output signals when applying the same input signals. We have not released those files yet due to some timing issue in our IBM library, but I have attached those files here for you to modify and use.

Yaosheng 

[Yaosheng Fu]

Sorry I attached an extra file async_fifo_mon.v.pyv, please ignore it.

Yaosheng

On Sunday, October 30, 2016 at 2:25:49 PM UTC-4, Zaid Manzoor Khan wrote:

[Zaid Manzoor Khan]

Hello Yaosheng

I was looking into Read me file that you provided and I was running the command in red below. I am getting a SIGDIE error, I was womdering if that is compatible with the 3rd Release because we are still working on 3rd Release.
Verification of a netlist requires following steps:

   1. Run RTL mini or full regression to generate stimuli files for
      netlist verification. To do that add
      -vcs_build_args=$DV_ROOT/verif/env/cmp/playback_dump.v option to
      the regression command and run. 

      For example, thread1_mini regression command will look like
      following for the SPARC level driver generation, 
     
      % sims -sim_type=vcs -group=thread1_mini -debussy \
        -vcs_build_args=$DV_ROOT/verif/env/cmp/playback_dump.v

Thanks

Zaid

--
You received this message because you are subscribed to a topic in the Google Groups "OpenPiton Discussion" group.
To unsubscribe from this topic, visit https://groups.google.com/d/topic/openpiton/yH3i8_VBxvk/unsubscribe.
To unsubscribe from this group and all its topics, send an email to openpiton+unsubscribe@googlegroups.com.
To post to this group, send email to open...@googlegroups.com.

To view this discussion on the web, visit https://groups.google.com/d/msgid/openpiton/59e6d58c-a54e-43c5-9231-f5df19a3501b%40googlegroups.com.

For more options, visit https://groups.google.com/d/optout.

[Yaosheng Fu]

Hi Zaid,

Due to some incompatibility with the released version, you may need to make a few changes:

1. thread1_mini is not supported in the released version, you can use tile1_mini or princeton-test (this is the smallest group) instead.

2. Use playback_dump_chip.v I attached earlier instead of playback_dump.v.

3. Modify the signals in playback_dump_chip.v from cmp_top.chip to cmp_top.system.chip.

4. Change the path of the ouput file stimuli.txt in playback_dump_chip.v

Please let me know if you have more questions.

Yaosheng

[Zaid Manzoor Khan]

Hello Yaosheng

I ran the below command now:
sims -sim_type=vcs -group=princeton-test -debussy -vcs_build_args=$DV_ROOT/verif/env/manycore/playback_dump_chip.v

I am attaching the log and the stimuli.txt file that is getting created, the simulaiton is failing. I changed the stimulit.txt path in my playback_dump_chip.v to this path /ece/home/khanx290/Desktop/OpenPiton/piton/verif/diag/princeton/stimuli.txt, is this the correct path for stimuli.txt to be given for the princeton-test group.

Also, i have left cmp_top unchanged because when I change it to cmp_top.system I get cross module reference Errors.

Thanks

Zaid

To view this discussion on the web, visit https://groups.google.com/d/msgid/openpiton/c4bcb3ee-b3dd-4ca0-b1d0-65f419ba908b%40googlegroups.com.

[Yaosheng Fu]

Could you try running sims -sim_type=vcs -group=princeton-test first to see whether it passes? Also make sure to clean up the build folder before a new simulation. Are you using the latest release version?

Yaosheng

[Zaid Manzoor Khan]

Hello

We are using the 3rd version since we have made many changes there and sims -sim_type=vcs -group=princeton-test is failing because of some change that we unknowingly made maybe.

Thanks

Zaid

To view this discussion on the web, visit https://groups.google.com/d/msgid/openpiton/fac17b13-3dc8-48bb-9be1-69855a463307%40googlegroups.com.

[Zaid Manzoor Khan]

Hello Yaosheng

So I was able to successfully run through first step of creating the stimuli.txt file.

Now i was trying to run through second and third steps in Read me file
I have created a flist file now with these files
1) sparc_core.mapped.v netlist

2) HVT.v

3) NVT.v

4) LVT.v
5) playback_driver_chip.v

And I ran this script after creating the flist file in manycore directory, Please check if this command is correct-
$VCS_HOME/bin/vcs -timescale=1ps/1ps -Xstrict=1 -notice  +vcsd -l compile.log -debug_all -f flist_zaid +vcs+initreg+random -sdf ${2}:${3}:${4} -full64 +neg_tchk -negdelay +vc+abstract +v2k +sdfverbose

I have attached the output of the above file in this email.

I am getting these Errors now :
Error-[URMI] Unresolved modules
playback_driver_chip.v, 151
"chip chip( .slew (1'b1),  .impsel1 (1'b1),  .impsel2 (1'b1),  .core_ref_clk (core_ref_clk),  .io_clk (io_clk),  .rst_n (chip_rst_n),  .pll_rst_n (pll_rst_n),  .clk_en (clk_en),  .async_mux (async_mux),  .pll_lock (pll_lock),  .pll_bypass (pll_bypass),  .pll_rangea (pll_rangea),  .clk_mux_sel (clk_mux_sel),  .oram_on (1'b0),  .oram_traffic_gen (1'b0),  .oram_dummy_gen (1'b0),  .jtag_clk (jtag_clk),  .jtag_rst_l (jtag_rst_l),  .jtag_modesel (jtag_modesel),  .jtag_datain (jtag_datain),  .jtag_dataout (jtag_dataout),  .intf_chip_data (intf_chip_data),  .intf_chip_channel (intf_chip_channel),  .intf_chip_credit_back (intf_chip_credit_back),  .chip_intf_data (chip_intf_data),  .chip_intf_channel (chip_intf_channel),  .chip_intf_credit_back (chip_intf_credit_b ... "
  Module definition of above instance is not found in the design.


Error-[URMI] Unresolved modules
sparc_core.mapped.v, 14700
"sram_1rw_128x78 regfile( .MEMCLK (rclk),  .RESET_N (n_0_net_),  .CE (n_1_net_),  .A (ctl_frf_addr),  .DIN (dp_frf_data),  .BW ({ctl_frf_wen[1], ctl_frf_wen[1], ctl_frf_wen[1], ctl_frf_wen[1], ctl_frf_wen[1], ctl_frf_wen[1], ctl_frf_wen[1], ctl_frf_wen[1], ctl_frf_wen[1], ctl_frf_wen[1], ctl_frf_wen[1], ctl_frf_wen[1], ctl_frf_wen[1], ctl_frf_wen[1], ctl_frf_wen[1], ctl_frf_wen[1], ctl_frf_wen[1], ctl_frf_wen[1], ctl_frf_wen[1], ctl_frf_wen[1], ctl_frf_wen[1], ctl_frf_wen[1], ctl_frf_wen[1], ctl_frf_wen[1], ctl_frf_wen[1], ctl_frf_wen[1], ctl_frf_wen[1], ctl_frf_wen[1], ctl_frf_wen[1], ctl_frf_wen[1], ctl_frf_wen[1], ctl_frf_wen[1], ctl_frf_wen[1], ctl_frf_wen[1], ctl_frf_wen[1], ctl_frf_wen[1], ctl_frf_wen[1], ctl_frf_wen[1], ctl_frf_wen, ctl_frf_wen[0] ... "
  Module definition of above instance is not found in the design.
..

..

So do you know how to resolve these? since there is no chip module definition anywhere.

Thanks

Zaid

[Yaosheng Fu]

Hi Zaid,

It seems you are only using a netlist of a sparc core instead of the entire chip. A chip is consist of one or more tiles, and each tile is consist of a core and other components such as L2 and NoC router. Therefore, you will not be able to find the module 'chip' in the netlist. If you only need to simulate a core, you need to modify the playback dump file to change the module to a core.

Besides, -sdf ${2}:${3}:${4} in your command should be replaced with -sdf min|typ|max:instance_name:file.sdf 

Best,

Yaosheng

[Zaid Manzoor Khan]

Hello Yaosheng

How did you run synthesis for Entire Chip?

When I run ./rsyn chip it errors out for me as an invalid option. But for tile and sparc it worked when I used this command - ./rsyn tile and ./rsyn sparc 

And its release 3, is it possible to release entire chip synthesis in Release 3?

Thanks

Zaid

To view this discussion on the web, visit https://groups.google.com/d/msgid/openpiton/e173800f-65ed-4e42-bb78-ef1b0e7ab517%40googlegroups.com.

[Zaid Manzoor Khan]

Hello Yaosheng

Can we use this method like this somehow?

"Synthesize just sparc_core and replace sparc_core.v with sparc_core netlist file. And then run this playback method on entire chip? So basically the chip tile in rtl and just the sparc core in tile will be netlist.

But when I tried doing that I got error because in chip.v file there is define.vh file included but that file is not present in the directory itself."

I was trying to do this way because I was not able to figure out a way to create a playback dump and driver files just for the sparc core because I dont know what signals to be made as vectors.

So if you can provide us with a dump and driver file for sparc core itself, i can try that method too.

Also, we have moved to latest release now to be on the same page with you guys.

Thanks

Zaid

[Yaosheng Fu]

Hi Zaid,

Synthesize the entire chip requires some hierarchical flow rather than simply using rsyn. The biggest unit rsyn can handle is a tile. If you just need to synthesis and simulate a sparc core, you can modify playback_dump.v and playback_driver.v to match the input and output signals for a core. When you dump signals, you are using rtl files of the entire chip, but when you replay with playback_driver.v, you only need to feed input signals and compare output signals to the sparc core netlist.

Yaosheng

[Zaid Manzoor Khan]

Hi Yaosheng,

So what I have understood is this, let me know if I understood it the right way:

1) I can use the same unchanged playback_dump.v that you gave to dump signals because as you are saying that we are using RTL files of the entire chip.

2) I can create a flist with these files in it : sparc_core netlist, playback_driver file and library used for synthesis (Also note that playback_driver will be the modified file in this for sparc_core netlist).

3) run the command build_gates <flist>

Let me know if that makes sense?

Thanks

Zaid

To view this discussion on the web, visit https://groups.google.com/d/msgid/openpiton/048a4efe-95b4-469c-ae6c-4b76a036ca91%40googlegroups.com.

[Yaosheng Fu]

Zaid,

1) You need to modify the playback_dump.v file because it's for the original OpenSPARC T1 and we have changed some input and output signals.

2) Correct

3) run the command build_gates <flist> min|typ|max instance_name file.sdf. The extra parameters are for SDF annotations.

Yaosheng 

[Zaid Manzoor Khan]

Hello Yaosheng

1) But the file playback_dump_chip.v which was provided by you  to me yesterday has those changes already right? so i can use playback_dump_chip.v as it is or not?

2) OK

3) Yes the README file is actually missing this sdf part in the command. Okay I will add this.

Thanks

Zaid

To view this discussion on the web, visit https://groups.google.com/d/msgid/openpiton/963317ff-7e15-4665-9604-9437113a2623%40googlegroups.com.

[Yaosheng Fu]

The file  playback_dump_chip.v only dumps the input and output signals of the chip module, but what you need are the input and output signals of the sparc core module. Therefore, u need to modify it. The original playback_dump.v file in the verif/env/manycore folder works for the sparc core module in the OpenSPARC T1 design, but since we modified the sparc core module with some different input and output signals, you cannot directly use that file either.

Yaosheng

[Zaid Manzoor Khan]

Okay that makes sense, but we are not yet familiar with the design so it would be difficult for us at this stahe to say what all signals we need to add or remove.

But still I had a look at the sparc_core just now and I saw that you have removed all these signals from the sparc_core now:(The one that I have commented).
So I have commented them but what new signals need to be added, I have no clue of that. So can you suggest me some way that I can follow from here?
wire [156:0] input_vector = {
    cmp_top.iop.sparc0.pcx_spc_grant_px,
    cmp_top.iop.sparc0.cpx_spc_data_rdy_cx2,
    cmp_top.iop.sparc0.cpx_spc_data_cx2,
    //cmp_top.iop.sparc0.cluster_cken,
    //cmp_top.iop.sparc0.cmp_grst_l,
    //cmp_top.iop.sparc0.cmp_arst_l,
    //cmp_top.iop.sparc0.ctu_tst_pre_grst_l,
    //cmp_top.iop.sparc0.adbginit_l,
    //cmp_top.iop.sparc0.gdbginit_l};

wire [129:0] output_vector = {
    cmp_top.iop.sparc0.spc_pcx_req_pq,
    cmp_top.iop.sparc0.spc_pcx_atom_pq,
    cmp_top.iop.sparc0.spc_pcx_data_pa};

Thanks

Zaid

To view this discussion on the web, visit https://groups.google.com/d/msgid/openpiton/9b5424b6-a538-46a2-9e8d-ecc2d1cb75e9%40googlegroups.com.

[Yaosheng Fu]

A simple way is to put all input and output signals to vectors except for clk signals. You can generate clk signals in an initial block similar to what the other dump files do.

Yaosheng

[Zaid Manzoor Khan]

Hello Yaosheng

I am not even able to perform first step of generating the stimuli. I have changed the playback_dump file but getting below errors:

I was able to run the same command in previous release but not in your latest rule.

Also, your READ ME talks about some /verif/env/cmp and /verif/gatesim but i cant see any of those too in the latest release.

[khanx290@ece-genesis build]$ sims -sim_type=vcs -group=princeton-test -debussy build_args=/home/khanx290/Desktop/OpenPiton_Release4/piton/verif/env/manycore/playback_dump.v
sims -sim_type=vcs -group=princeton-test -debussy build_args=/home/khanx290/Desktop/OpenPiton_Release4/piton/verif/env/manycore/playback_dump.v
sims: ====================================================
sims:   Simulation Script for OpenPiton
sims:   Modified by Princeton University on June 9th, 2015
sims: ====================================================
sims: ====================================================
sims:   Simulation Script for OpenSPARC T1
sims:   Copyright (c) 2001-2006 Sun Microsystems, Inc.
sims:   All rights reserved.
sims: ====================================================
sims: start_time Thu Nov  3 12:15:24 CDT 2016
sims: running on ece-genesis
sims: uname is Linux ece-genesis 2.6.32-573.18.1.el6.x86_64 #1 SMP Wed Jan 6 11:20:49 EST 2016 x86_64 x86_64 x86_64 GNU/Linux
sims: version 1.262
sims: dv_root /home/khanx290/Desktop/OpenPiton_Release4//piton
sims: model_dir /home/khanx290/Desktop/OpenPiton_Release4//build
sims: tre_search /ece/home/khanx290/Desktop/OpenPiton_Release4/build/2016_11_03_7/tre/sims.iver
sims: Frozen tre_search /home/khanx290/Desktop/OpenPiton_Release4//piton/tools/env/tools.iver
sims: processing diaglist /home/khanx290/Desktop/OpenPiton_Release4//piton/verif/diag/master_diaglist () ..
sims: Caught a SIGDiagList: Diag # appears outside any group.
File=/ece/home/khanx290/Desktop/OpenPiton_Release4/build/2016_11_03_7/master_diaglist.princeton-test, Line=1
 at /home/khanx290/Desktop/OpenPiton_Release4/piton/tools/perlmod/DiagList/1.11/lib/site_perl/5.8.0/DiagList/Objects.pm line 206

Thanks

Zaid

On Wed, Nov 2, 2016 at 10:02 PM, Zaid Manzoor Khan <khan...@umn.edu> wrote:

Sure sounds good.

I will try out that tomorrow and will let you know if i face any issue.

Also, a gentle reminder that we are having a skype call tomorrow at 1 pm Central Time Zone (our time) and 2 pm Eastern Time Zone (your time)

Thanks

Zaid

To view this discussion on the web, visit https://groups.google.com/d/msgid/openpiton/87a57275-763a-417f-a1b9-a2f9d43cd64a%40googlegroups.com.

[Zaid Manzoor Khan]

+ Addding OpenPiton Group

On Fri, Nov 4, 2016 at 9:01 PM, Zaid Manzoor Khan <khan...@umn.edu> wrote:

Yaosheng,

There were some bugs in my driver files which I have updated and attached my file here.

I notice that there are total 86606 (86 K Cycles) out of which I see 20498 cycles mismatches (20 K Cycles).

I have attached my files again here and also stimuli1.log for review.

May be we are not dealing with clock correctly so thats why I would like you to have one look over our files please.

Thanks

Zaid

On Fri, Nov 4, 2016 at 1:21 PM, Zaid Manzoor Khan <khan...@umn.edu> wrote:

Hello Yaosheng

I am attaching the playback_dump and playback_driver file for sparc core that i created. I am also attaching the stimuli.log that I got after the simulation.

Please review the dump and driver file for us whenever you get time to do so because I am getting mismatches.

Also, i noticed that sparc_core is just a kind of wrapper around sparc now , so I created these files for sparc_core basically and not the sparc because the netlist that we got from rsyn is for sparc_core.

Thanks

Zaid

On Fri, Nov 4, 2016 at 11:13 AM, Zaid Manzoor Khan <khan...@umn.edu> wrote:

Hello Yaosheng,
So i was able to run the simulation for sparc_core yesterday night. I have got some mismatches.
I will look into that today and will let you know if i face any issues.
Thanks!
Zaid

On Nov 4, 2016 10:39 AM, "Yaosheng Fu" <fuy...@gmail.com> wrote:

It should be cmp_top.system.chip.tile0.core.sparc0.pcx_spc_grant_px.

Yaosheng

On Thu, Nov 3, 2016 at 3:36 PM, Zaid Manzoor Khan <khan...@umn.edu> wrote:

Hello Yaosheng

Is this the correct Hierarchy? cmp_top.system.chip.tile.sparc0.pcx_spc_grant_px,

Because, I am getting cross module reference resoliution errors as :
Error-[XMRE] Cross-module reference resolution error
/home/khanx290/Desktop/OpenPiton_Release4/piton/verif/env/manycore/playback_dump.v, 49
  Error found while trying to resolve cross-module reference.
  token 'tile'.  Originating module 'playback_dump', first module hit
  'cmp_top'.
  Source info: assign input_vector =
  {cmp_top.system.chip.tile.sparc0.pcx_spc_grant_px,
  cmp_top.system.chip.tile.sparc0.cpx_spc_data_rdy_cx2,
  cmp_top.system.chip.tile.sparc0.cpx_spc_data_cx2,
  cmp_top.system.chip.tile.sparc0.cmp_arst_l,
  cmp_top.system.chip.tile.sparc0.rtap_srams_bist_command,
  cmp_top.system.chip.tile.sparc0.rtap_srams_bist_data,
  cmp_top.system.chip.tile.sparc0.rtap_core_val,
  cmp_top.system.chip.tile.sparc0.rtap_core_threadid,
  cmp_top.system.chip.tile.sparc0.rtap_core_id,
  cmp_top.system.chip.tile.sparc0.rtap_core_data};

Thanks

Zaid

On Thu, Nov 3, 2016 at 2:18 PM, Zaid Manzoor Khan <khan...@umn.edu> wrote:

Hello All

I have resolved this Error:sims: Caught a SIGDiagList: Diag # appears outside any group.

File=/ece/home/khanx290/Desktop/OpenPiton_Release4/build/2016_11_03_7/master_diaglist.princeton-test, Line=1
 at /home/khanx290/Desktop/OpenPiton_Release4/piton/tools/perlmod/DiagList/1.11/lib/site_perl/5.8.0/DiagList/Objects.pm line 206

It was due to extra '/' in the end of PITON_ROOT path.

Thanks

Zaid

On Thu, Nov 3, 2016 at 12:49 PM, Zaid Manzoor Khan <khan...@umn.edu> wrote:

Yes this is also not working sims -sim_type=vcs -group=princeton-test first

 Nov 3, 2016 12:37 PM, "Yaosheng Fu" <fuy...@gmail.com> wrote:

It should work, could you try sims -sim_type=vcs -group=princeton-test first?

Yaosheng

On Thu, Nov 3, 2016 at 1:34 PM, Zaid Manzoor Khan <khan...@umn.edu> wrote:

Hello Yaosheng

I tried this command also:
sims -sim_type=vcs -group=princeton-test -vcs_build_args=/home/khanx290/Desktop/OpenPiton_Release4/piton/verif/env/manycore/playback_dump.v

But this also giving same error.

Do i have to change the above command for latest release?

Thanks

Zaid

[Zaid Manzoor Khan]

Hello All

I notice two major issues in your driver and dump scripts:

1) Synchronization Issue

I am noticing that there is some timing problem with your playback driver files thats why my sparc_core tests playback is failing.

When the playback_driver script picks up output_vector_ref from the stimuli.txt file it starts picking up the values after delay of two cycles.

2) Treating X on RTL as a match always.

Also, i notice that your script is written in such a way that whenever the RTL has dumped 'x' then playback driver treats that as a match irrespective of whatever the Netlist output is. Is there any reason for doing that?

Please comment on these issues because our work is kind of stuck at this point as of now because we are not able to even verify whether the Netlist we got is functionally correct or not.

Thanks

Zaid

[Yaosheng Fu]

1) You need to make sure the input vector of RTL simulation and gate-level simulation to be exact the same. This can be usually done by check clock and reset signals. The clock signal on the original dump file might not match the latest version.

2)X signals are usually un-initialized signals and should not affect the accuracy of the output results.

Yaosheng

...