Timing Violations in implementation

[Andreas Wrisley]

Hi all,

I'm trying to create a bitstream to load to my Genesys2 board, but run into problem I don't know how to handle. I was hoping to get started by building an initial dual core design and then as I learn more, try to modify it during my PhD studies.

I also have problems with building a simulation.

I updated my_top.cpp by adding const to extern "C" void init_jbus_model_call(const char *str, int oram) and also updating the -march with zicsr since my GCC is 13.2

Running

$ sims -sys=manycore -x_tiles=1 -y_tiles=1 -vlt_build -ariane

gives me the following error

%Error: /home/andlo47/development/openpiton3/piton/design/chip/tile/ariane/core/cache_subsystem/wt_dcache_wbuffer.sv:486:71: Extracting 8 bits from only 1 bit number

I use Vivado 2023.2, verilator 4.106 and the latest commit on openpiton-dev (41a14a05010).

When building the bitstream I use the following command:

$ protosyn -b genesys2 -d system --core=ariane --x_tiles=2 --y_tiles=1 --uart-dmw ddr

I do get a bitstream, but get an error about timing violations

[INFO]  protosyn,2.5:708: ----- System Configuration -----
[INFO]  protosyn,2.5:726: x_tiles   = 2
[INFO]  protosyn,2.5:727: y_tiles   = 1
[INFO]  protosyn,2.5:728: num_tiles = 2
[INFO]  protosyn,2.5:735: core      = ariane
[INFO]  protosyn,2.5:738: defining RTL_TILE0
[INFO]  protosyn,2.5:738: defining RTL_TILE1
[INFO]  protosyn,2.5:769: setenv RTL_ARIANE0
[INFO]  protosyn,2.5:769: setenv RTL_ARIANE1
[INFO]  protosyn,2.5:790: network   = 2dmesh_config
[INFO]  protosyn,2.5:794: l15 size  = 8192
[INFO]  protosyn,2.5:795: l15 assoc = 4
[INFO]  protosyn,2.5:796: l1d size  = 8192
[INFO]  protosyn,2.5:797: l1d assoc = 4
[INFO]  protosyn,2.5:798: l1i size  = 16384
[INFO]  protosyn,2.5:799: l1i assoc = 4
[INFO]  protosyn,2.5:800: l2  size  = 65536
[INFO]  protosyn,2.5:801: l2  assoc = 4
[INFO]  protosyn,2.5:820: ---- Additional RTL Defines ----
[INFO]  protosyn,2.5:823: NO_RTL_CSM
[INFO]  protosyn,2.5:823: PITON_FPGA_MC_DDR3
[INFO]  protosyn,2.5:823: PITONSYS_MEM_ZEROER
[INFO]  protosyn,2.5:823: PITON_FPGA_SD_BOOT
[INFO]  protosyn,2.5:823: PITONSYS_UART_BOOT
[INFO]  protosyn,2.5:823: PITON_NO_CHIP_BRIDGE
[INFO]  protosyn,2.5:823: PITON_UART16550
[INFO]  protosyn,2.5:823: PITON_FPGA_ETHERNETLITE
[INFO]  protosyn,2.5:825: --------------------------------
[INFO]  protosyn,2.5:894: Generating UART init sequence
[INFO]  protosyn,2.5:637: Using core clock frequency: 66.667 MHz
[INFO]  protosyn,2.5:289: Building a project for design 'system' on board 'genesys2'
[INFO]  protosyn,2.5:334: Running FPGA implementation down to bitstream generation
[INFO]  protosyn,2.5:947: Checking Project Build results
[INFO]  fpga_lib.py:348: Project was build successfully!
[INFO]  protosyn,2.5:954: Checking Project Implementation results
[ERROR] fpga_lib.py:385: Implemented design has timing violations!
[ERROR] fpga_lib.py:386: Check: /home/andlo47/development/openpiton3/build/genesys2/system/genesys2_system/genesys2_system.runs/impl_1/system_timing_summary_routed.rpt

In the system_timing_summary_routed.rpt there are several critical warnings:

TIMING-4   Critical Warning  Invalid primary clock redefinition on a clock tree 2          
TIMING-6   Critical Warning  No common primary clock between related clocks 2          
TIMING-7   Critical Warning  No common node between related clocks 2          
TIMING-14  Critical Warning  LUT on the clock tree 1          
TIMING-27  Critical Warning  Invalid primary clock on hierarchical pin 2           

Any help on either of these issues would be much appreciated.

Regards,

/Andreas Wrisley, Linköping University

[Jonathan Balkind]

Hi Andreas,

Glad to hear from you! What you're seeing isn't entirely unexpected.

Regarding verilator, try v4.110. I helped another user the other day who found this version worked, having seen the same error you're seeing on an earlier one.

Regarding vivado, if you grep for VIOL in the timing report, what order of magnitude are the timing violations? In general, we do see some minor timing violations for dual core on genesys2 but the design will still work if the scale is small enough.

Thanks,

Jon

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[Andreas Wrisley]

Hi Jon,

Thanks for the quick reply. There are 10 violations between -0.501ns to -0.591ns. Would those be considered small enough?

Verilator v4.110 works, thanks a lot!

/Andreas

[Jonathan Balkind]

My experience has been that it will still work at that scale. Particularly if the failures are in the FPU, which they usually are. Vivado's retimer is pretty weak.

Thanks,

Jon

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[Andreas Wrisley]

Ok, good to know. They are all in the FPU.

/Andreas