NEW IP test

[SALMEN BELGACEM]

Hello everyone,

I have added a new axi wrapped IP to openpiton and instantiated it in the uart_top module and passed the core_axi_* wires to it and the bitstream was generated successfully ,how can i test it and verify if my data is reaching the IP correctly ? 

Thanks.

[Jonathan Balkind]

Instantiating the IP inside uart_top isn't really how I would recommend to connect an IP. Rather, you probably want to modify devices_ariane.xml to include another device (e.g. named device1), then the infrastructure will create new noc wires (with device1 in the name of each wire) in chipset_impl.tmp.v based on the contents of chipset_impl.v.pyv and devices_ariane.xml. To those noc wires you can then instantiate your own noc_axilite_bridge. If you replace uart_top's wires then there will be a lot of other issues that you will have to unravel.

As for testing, are you running in simulation or on FPGA? That would affect my answer.

Thanks,

Jon

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[Jim Andronikou]

Hello.

I am trying to instantiate a new module in the design. I added it to xml and instantiate it in  chipset_impl.v.pyv. 

The project generates the correct wires and the module is connected. However, when I boot Linux, the bootROM uart prints the message with errors and the booting stops. If I remove the SD from XML or my new module, then design works correctly and fully boots Linux. I think that somehow the instantiation creates errors to NoC, is that possible? Do I have to modify the total number of devices (if there is such a variable)?

Thank you!

Dimitris Andronikou

[Jonathan Balkind]

I think I would need to know more about what you did and what you're seeing to give a confident answer. Based on my understanding of what you did say, I would suggest you check the address ranges that you allocated in the XML to make sure that they aren't overlapping in unexpected ways.

Thanks,

Jon

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