OpenPiton+Ariane memory map: is devices_ariane.xml the canonical reference?

[Radhe shyam]

Hi everyone, 

I'm Radheshyam, a student working on the "Generic MinimumLinuxBoot for RTL Simulations" GSoC 2026 project idea. I've been doing pre-GSoC experiments and have a question about the Ariane memory map.

I'm building a tool to extract Linux state from QEMU and inject it into OpenPiton's Verilator simulation. For this to work, the QEMU virt machine's memory map must match OpenPiton+Ariane's layout. I found piton/design/xilinx/genesys2/devices_ariane.xml — is this the canonical reference for Ariane peripheral addresses (CLINT, PLIC, UART, DRAM)?

Specifically:

1. Does the Verilator simulation use the same addresses as the Genesys2 FPGA config, or is there a separate map for simulation?
2. I confirmed DRAM starts at 0x80000000 — do CLINT/PLIC/UART also match the QEMU virt defaults (0x02000000, 0x0C000000, 0x10000000)?

Thanks!

[Jonathan Balkind]

Hi Radheshyam,

Yes, there is a separate map for simulation, in piton/verif/env/manycore/devices_ariane.xml

The peripherals are generally kept in the same location across our target platforms but they differ from QEMU as you'll see.

Thanks,

Jon

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