Hii everyone,
I'm new to OpenPiton manycore framework, I'm trying to design the OpenPiton architecture with integration of new IP design into it. I have simulated the Verilog codes of OpenPiton architecture using Vivado 2023.2, but in vivado I'm getting some the errors that it couldn't add embedded python files to L2 and L15 cache.
I think in vivado we can only simulate Verilog files with the .v extension, it wont take other extension files. soo for the students which tool is best for designing.
As OpenPiton is the great framework, Soo i wanted to design the risc-v processor using the opensource with the integration of new IP into it.
soo can anyone please help me out with the designing part.