Spresense smp test

[Xiang Xiao]

Hi Ishikawa and Alin,

Do you have any SMP tool or test flow to verify the SMP performance and stability? We are evaluating NuttX SMP support on Spresense board.

Thanks

Xiang

[Alin Jerpelea]

HI Xiang,

unfortunately the Spresense board needs a new bootloader (1.5) to be able to use the SMP feature.

The new bootloader will be released ASAP.

Regards

Alin

[Xiang Xiao]

Could you share SMP tool for either performance or stability? So we can do some preparation before the new bootloader release.

[Masayuki Ishikawa]

Hi, Xaing,

Thanks for having interest in NuttX SMP support on Sony Spresense.

As Alin wrote, you need a new boot loader which will be released soon.

Regarding SMP tools, I usually use apps/testing/smp and apps/testing/ostest.

You can also use telnetd with USB-RNDIS or Wi-Fi (which needs GS2200M module) to login to Spresense.

Another useful tool is apps/system/taskset which is used to change CPU affinity.

Regards,

Masayuki Ishikawa

2019年11月22日(金) 18:13 Xiang Xiao <xiaoxia...@gmail.com>:

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[spudaneco]

There is also special SMP instrumentation in the OS based on the sched_nute_* interfaces.  There is also a monitor in apps/ for sumping the sched_note_* output.  

The typical SMP faikure is a hang and this instrumenatation is most useful for getting the events leading to the hang.

Sent from Samsung tablet.

[patacongo]

Too many typos, sorry.  That happens especially when I use a tablet.

 

There is also special SMP instrumentation in the OS based on the sched_nute_* interfaces.  There is also a monitor in apps/ for dumping the sched_note_* output.  

The typical SMP failure is a hang and this instrumentation is most useful for getting the events leading to the hang.

That monitor I mentioned is at apps/system/sched_note.  It requires buffered sched_note data which makes it less useful for debugging hangs.  Running multiple copies of ostest on multiple CPUs realy beats the system pretty well.

On thing that important to note:  Ishikawa-san has shown that if you have no data cache, then the use of SMP on more than a couple of CPUs is not helpful due to RAM access collisions.  See https://nuttx.events/wp-content/uploads/2019/11/MIshikawa_nx2019.pdf

And, if you have data cache, then cache coherency becomes an issue.

Greg

[Xiang Xiao]

Thanks for the detaied info, I will try it.

[Gregory Nutt]

On thing that important to note:  Ishikawa-san has shown that if you have no data cache, then the use of SMP on more than a couple of CPUs is not helpful due to RAM access collisions.  See https://nuttx.events/wp-content/uploads/2019/11/MIshikawa_nx2019.pdf

I suppose that depends in part on the memory architecture as well.  When Ishikawa-san demonstrated the issues he was running two copies of the same mrmory-intensive application on two CPUs.  Perhaps the interference would not be so great if doing things in unrelated memory.  Otherwise, AMP in a common memory space would have the same issues, I would think.